1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/sys_proto.h> 14 #include <malloc.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/errno.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/imx-common/sata.h> 21 #include <asm/imx-common/boot_mode.h> 22 #include <asm/imx-common/video.h> 23 #include <mmc.h> 24 #include <fsl_esdhc.h> 25 #include <micrel.h> 26 #include <miiphy.h> 27 #include <netdev.h> 28 #include <asm/arch/crm_regs.h> 29 #include <asm/arch/mxc_hdmi.h> 30 #include <i2c.h> 31 #include <input.h> 32 #include <netdev.h> 33 #include <usb/ehci-fsl.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 37 38 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 40 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 44 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 45 46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 48 49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 51 52 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 54 55 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 57 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 58 59 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ 60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 61 PAD_CTL_SRE_SLOW) 62 63 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 65 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 66 67 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 68 69 int dram_init(void) 70 { 71 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); 72 73 return 0; 74 } 75 76 static iomux_v3_cfg_t const uart1_pads[] = { 77 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 78 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 79 }; 80 81 static iomux_v3_cfg_t const uart2_pads[] = { 82 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 83 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 84 }; 85 86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 87 88 /* I2C1, SGTL5000 */ 89 static struct i2c_pads_info i2c_pad_info0 = { 90 .scl = { 91 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 92 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 93 .gp = IMX_GPIO_NR(3, 21) 94 }, 95 .sda = { 96 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 97 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 98 .gp = IMX_GPIO_NR(3, 28) 99 } 100 }; 101 102 /* I2C2 Camera, MIPI */ 103 static struct i2c_pads_info i2c_pad_info1 = { 104 .scl = { 105 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 106 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 107 .gp = IMX_GPIO_NR(4, 12) 108 }, 109 .sda = { 110 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 111 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 112 .gp = IMX_GPIO_NR(4, 13) 113 } 114 }; 115 116 /* I2C3, J15 - RGB connector */ 117 static struct i2c_pads_info i2c_pad_info2 = { 118 .scl = { 119 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, 120 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, 121 .gp = IMX_GPIO_NR(1, 5) 122 }, 123 .sda = { 124 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 125 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, 126 .gp = IMX_GPIO_NR(7, 11) 127 } 128 }; 129 130 static iomux_v3_cfg_t const usdhc2_pads[] = { 131 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 }; 138 139 static iomux_v3_cfg_t const usdhc3_pads[] = { 140 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 147 }; 148 149 static iomux_v3_cfg_t const usdhc4_pads[] = { 150 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 155 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 156 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 157 }; 158 159 static iomux_v3_cfg_t const enet_pads1[] = { 160 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 161 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 162 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 163 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 164 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 165 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 166 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 167 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 168 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 169 /* pin 35 - 1 (PHY_AD2) on reset */ 170 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 171 /* pin 32 - 1 - (MODE0) all */ 172 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 /* pin 31 - 1 - (MODE1) all */ 174 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 /* pin 28 - 1 - (MODE2) all */ 176 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 /* pin 27 - 1 - (MODE3) all */ 178 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 180 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 181 /* pin 42 PHY nRST */ 182 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 183 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 184 }; 185 186 static iomux_v3_cfg_t const enet_pads2[] = { 187 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 188 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 189 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 190 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 191 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 192 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 193 }; 194 195 static iomux_v3_cfg_t const misc_pads[] = { 196 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), 197 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), 198 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), 199 /* OTG Power enable */ 200 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), 201 }; 202 203 /* wl1271 pads on nitrogen6x */ 204 static iomux_v3_cfg_t const wl12xx_pads[] = { 205 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) 206 | MUX_PAD_CTRL(WEAK_PULLDOWN), 207 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) 208 | MUX_PAD_CTRL(OUTPUT_40OHM), 209 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) 210 | MUX_PAD_CTRL(OUTPUT_40OHM), 211 }; 212 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 213 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) 214 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) 215 216 /* Button assignments for J14 */ 217 static iomux_v3_cfg_t const button_pads[] = { 218 /* Menu */ 219 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 220 /* Back */ 221 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 222 /* Labelled Search (mapped to Power under Android) */ 223 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 224 /* Home */ 225 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 226 /* Volume Down */ 227 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 228 /* Volume Up */ 229 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 230 }; 231 232 static void setup_iomux_enet(void) 233 { 234 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ 235 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ 236 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 237 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 238 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 239 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 240 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 241 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 242 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 243 244 /* Need delay 10ms according to KSZ9021 spec */ 245 udelay(1000 * 10); 246 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ 247 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ 248 249 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 250 udelay(100); /* Wait 100 us before using mii interface */ 251 } 252 253 static iomux_v3_cfg_t const usb_pads[] = { 254 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 255 }; 256 257 static void setup_iomux_uart(void) 258 { 259 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 260 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 261 } 262 263 #ifdef CONFIG_USB_EHCI_MX6 264 int board_ehci_hcd_init(int port) 265 { 266 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 267 268 /* Reset USB hub */ 269 gpio_direction_output(IMX_GPIO_NR(7, 12), 0); 270 mdelay(2); 271 gpio_set_value(IMX_GPIO_NR(7, 12), 1); 272 273 return 0; 274 } 275 276 int board_ehci_power(int port, int on) 277 { 278 if (port) 279 return 0; 280 gpio_set_value(GP_USB_OTG_PWR, on); 281 return 0; 282 } 283 284 #endif 285 286 #ifdef CONFIG_FSL_ESDHC 287 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 288 {USDHC3_BASE_ADDR}, 289 {USDHC4_BASE_ADDR}, 290 }; 291 292 int board_mmc_getcd(struct mmc *mmc) 293 { 294 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 295 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) : 296 IMX_GPIO_NR(2, 6); 297 298 gpio_direction_input(gp_cd); 299 return !gpio_get_value(gp_cd); 300 } 301 302 int board_mmc_init(bd_t *bis) 303 { 304 s32 status = 0; 305 u32 index = 0; 306 307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 308 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 309 310 usdhc_cfg[0].max_bus_width = 4; 311 usdhc_cfg[1].max_bus_width = 4; 312 313 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 314 switch (index) { 315 case 0: 316 imx_iomux_v3_setup_multiple_pads( 317 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 318 break; 319 case 1: 320 imx_iomux_v3_setup_multiple_pads( 321 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 322 break; 323 default: 324 printf("Warning: you configured more USDHC controllers" 325 "(%d) then supported by the board (%d)\n", 326 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 327 return status; 328 } 329 330 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 331 } 332 333 return status; 334 } 335 #endif 336 337 #ifdef CONFIG_MXC_SPI 338 static iomux_v3_cfg_t const ecspi1_pads[] = { 339 /* SS1 */ 340 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 341 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 342 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 343 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 344 }; 345 346 static void setup_spi(void) 347 { 348 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 349 ARRAY_SIZE(ecspi1_pads)); 350 } 351 #endif 352 353 int board_phy_config(struct phy_device *phydev) 354 { 355 /* min rx data delay */ 356 ksz9021_phy_extended_write(phydev, 357 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 358 /* min tx data delay */ 359 ksz9021_phy_extended_write(phydev, 360 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 361 /* max rx/tx clock delay, min rx/tx control */ 362 ksz9021_phy_extended_write(phydev, 363 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 364 if (phydev->drv->config) 365 phydev->drv->config(phydev); 366 367 return 0; 368 } 369 370 int board_eth_init(bd_t *bis) 371 { 372 uint32_t base = IMX_FEC_BASE; 373 struct mii_dev *bus = NULL; 374 struct phy_device *phydev = NULL; 375 int ret; 376 377 setup_iomux_enet(); 378 379 #ifdef CONFIG_FEC_MXC 380 bus = fec_get_miibus(base, -1); 381 if (!bus) 382 return 0; 383 /* scan phy 4,5,6,7 */ 384 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 385 if (!phydev) { 386 free(bus); 387 return 0; 388 } 389 printf("using phy at %d\n", phydev->addr); 390 ret = fec_probe(bis, -1, base, bus, phydev); 391 if (ret) { 392 printf("FEC MXC: %s:failed\n", __func__); 393 free(phydev); 394 free(bus); 395 } 396 #endif 397 398 #ifdef CONFIG_CI_UDC 399 /* For otg ethernet*/ 400 usb_eth_initialize(bis); 401 #endif 402 return 0; 403 } 404 405 static void setup_buttons(void) 406 { 407 imx_iomux_v3_setup_multiple_pads(button_pads, 408 ARRAY_SIZE(button_pads)); 409 } 410 411 #if defined(CONFIG_VIDEO_IPUV3) 412 413 static iomux_v3_cfg_t const backlight_pads[] = { 414 /* Backlight on RGB connector: J15 */ 415 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 416 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) 417 418 /* Backlight on LVDS connector: J6 */ 419 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 420 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) 421 }; 422 423 static iomux_v3_cfg_t const rgb_pads[] = { 424 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 425 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, 426 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, 427 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, 428 MX6_PAD_DI0_PIN4__GPIO4_IO20, 429 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, 430 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, 431 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, 432 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, 433 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, 434 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, 435 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, 436 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, 437 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, 438 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, 439 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, 440 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, 441 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, 442 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, 443 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, 444 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, 445 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, 446 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, 447 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, 448 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, 449 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, 450 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, 451 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, 452 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, 453 }; 454 455 static void do_enable_hdmi(struct display_info_t const *dev) 456 { 457 imx_enable_hdmi_phy(); 458 } 459 460 static int detect_i2c(struct display_info_t const *dev) 461 { 462 return ((0 == i2c_set_bus_num(dev->bus)) 463 && 464 (0 == i2c_probe(dev->addr))); 465 } 466 467 static void enable_lvds(struct display_info_t const *dev) 468 { 469 struct iomuxc *iomux = (struct iomuxc *) 470 IOMUXC_BASE_ADDR; 471 u32 reg = readl(&iomux->gpr[2]); 472 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 473 writel(reg, &iomux->gpr[2]); 474 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 475 } 476 477 static void enable_rgb(struct display_info_t const *dev) 478 { 479 imx_iomux_v3_setup_multiple_pads( 480 rgb_pads, 481 ARRAY_SIZE(rgb_pads)); 482 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 483 } 484 485 struct display_info_t const displays[] = {{ 486 .bus = -1, 487 .addr = 0, 488 .pixfmt = IPU_PIX_FMT_RGB24, 489 .detect = detect_hdmi, 490 .enable = do_enable_hdmi, 491 .mode = { 492 .name = "HDMI", 493 .refresh = 60, 494 .xres = 1024, 495 .yres = 768, 496 .pixclock = 15385, 497 .left_margin = 220, 498 .right_margin = 40, 499 .upper_margin = 21, 500 .lower_margin = 7, 501 .hsync_len = 60, 502 .vsync_len = 10, 503 .sync = FB_SYNC_EXT, 504 .vmode = FB_VMODE_NONINTERLACED 505 } }, { 506 .bus = 2, 507 .addr = 0x4, 508 .pixfmt = IPU_PIX_FMT_LVDS666, 509 .detect = detect_i2c, 510 .enable = enable_lvds, 511 .mode = { 512 .name = "Hannstar-XGA", 513 .refresh = 60, 514 .xres = 1024, 515 .yres = 768, 516 .pixclock = 15385, 517 .left_margin = 220, 518 .right_margin = 40, 519 .upper_margin = 21, 520 .lower_margin = 7, 521 .hsync_len = 60, 522 .vsync_len = 10, 523 .sync = FB_SYNC_EXT, 524 .vmode = FB_VMODE_NONINTERLACED 525 } }, { 526 .bus = 2, 527 .addr = 0x38, 528 .pixfmt = IPU_PIX_FMT_LVDS666, 529 .detect = detect_i2c, 530 .enable = enable_lvds, 531 .mode = { 532 .name = "wsvga-lvds", 533 .refresh = 60, 534 .xres = 1024, 535 .yres = 600, 536 .pixclock = 15385, 537 .left_margin = 220, 538 .right_margin = 40, 539 .upper_margin = 21, 540 .lower_margin = 7, 541 .hsync_len = 60, 542 .vsync_len = 10, 543 .sync = FB_SYNC_EXT, 544 .vmode = FB_VMODE_NONINTERLACED 545 } }, { 546 .bus = 2, 547 .addr = 0x48, 548 .pixfmt = IPU_PIX_FMT_RGB666, 549 .detect = detect_i2c, 550 .enable = enable_rgb, 551 .mode = { 552 .name = "wvga-rgb", 553 .refresh = 57, 554 .xres = 800, 555 .yres = 480, 556 .pixclock = 37037, 557 .left_margin = 40, 558 .right_margin = 60, 559 .upper_margin = 10, 560 .lower_margin = 10, 561 .hsync_len = 20, 562 .vsync_len = 10, 563 .sync = 0, 564 .vmode = FB_VMODE_NONINTERLACED 565 } } }; 566 size_t display_count = ARRAY_SIZE(displays); 567 568 int board_cfb_skip(void) 569 { 570 return NULL != getenv("novideo"); 571 } 572 573 static void setup_display(void) 574 { 575 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 576 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 577 int reg; 578 579 enable_ipu_clock(); 580 imx_setup_hdmi(); 581 /* Turn on LDB0,IPU,IPU DI0 clocks */ 582 reg = __raw_readl(&mxc_ccm->CCGR3); 583 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 584 writel(reg, &mxc_ccm->CCGR3); 585 586 /* set LDB0, LDB1 clk select to 011/011 */ 587 reg = readl(&mxc_ccm->cs2cdr); 588 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 589 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 590 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 591 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 592 writel(reg, &mxc_ccm->cs2cdr); 593 594 reg = readl(&mxc_ccm->cscmr2); 595 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 596 writel(reg, &mxc_ccm->cscmr2); 597 598 reg = readl(&mxc_ccm->chsccdr); 599 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 600 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 601 writel(reg, &mxc_ccm->chsccdr); 602 603 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 604 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 605 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 606 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 607 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 608 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 609 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 610 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 611 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 612 writel(reg, &iomux->gpr[2]); 613 614 reg = readl(&iomux->gpr[3]); 615 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK 616 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 617 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 618 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 619 writel(reg, &iomux->gpr[3]); 620 621 /* backlights off until needed */ 622 imx_iomux_v3_setup_multiple_pads(backlight_pads, 623 ARRAY_SIZE(backlight_pads)); 624 gpio_direction_input(LVDS_BACKLIGHT_GP); 625 gpio_direction_input(RGB_BACKLIGHT_GP); 626 } 627 #endif 628 629 static iomux_v3_cfg_t const init_pads[] = { 630 /* SGTL5000 sys_mclk */ 631 NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), 632 633 /* J5 - Camera MCLK */ 634 NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM), 635 636 /* wl1271 pads on nitrogen6x */ 637 /* WL12XX_WL_IRQ_GP */ 638 NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), 639 /* WL12XX_WL_ENABLE_GP */ 640 NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), 641 /* WL12XX_BT_ENABLE_GP */ 642 NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), 643 /* USB otg power */ 644 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM), 645 NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM), 646 NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM), 647 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM), 648 NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM), 649 }; 650 651 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 652 653 static unsigned gpios_out_low[] = { 654 /* Disable wl1271 */ 655 IMX_GPIO_NR(6, 15), /* disable wireless */ 656 IMX_GPIO_NR(6, 16), /* disable bluetooth */ 657 IMX_GPIO_NR(3, 22), /* disable USB otg power */ 658 IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */ 659 IMX_GPIO_NR(1, 8), /* ov5642 reset */ 660 }; 661 662 static unsigned gpios_out_high[] = { 663 IMX_GPIO_NR(1, 6), /* ov5642 powerdown */ 664 IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */ 665 }; 666 667 static void set_gpios(unsigned *p, int cnt, int val) 668 { 669 int i; 670 671 for (i = 0; i < cnt; i++) 672 gpio_direction_output(*p++, val); 673 } 674 675 int board_early_init_f(void) 676 { 677 setup_iomux_uart(); 678 679 set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1); 680 set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); 681 gpio_direction_input(WL12XX_WL_IRQ_GP); 682 683 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); 684 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); 685 setup_buttons(); 686 687 #if defined(CONFIG_VIDEO_IPUV3) 688 setup_display(); 689 #endif 690 return 0; 691 } 692 693 /* 694 * Do not overwrite the console 695 * Use always serial for U-Boot console 696 */ 697 int overwrite_console(void) 698 { 699 return 1; 700 } 701 702 int board_init(void) 703 { 704 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 705 706 clrsetbits_le32(&iomuxc_regs->gpr[1], 707 IOMUXC_GPR1_OTG_ID_MASK, 708 IOMUXC_GPR1_OTG_ID_GPIO1); 709 710 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); 711 712 /* address of boot parameters */ 713 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 714 715 #ifdef CONFIG_MXC_SPI 716 setup_spi(); 717 #endif 718 imx_iomux_v3_setup_multiple_pads( 719 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 720 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 721 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 722 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 723 724 #ifdef CONFIG_CMD_SATA 725 setup_sata(); 726 #endif 727 728 return 0; 729 } 730 731 int checkboard(void) 732 { 733 if (gpio_get_value(WL12XX_WL_IRQ_GP)) 734 puts("Board: Nitrogen6X\n"); 735 else 736 puts("Board: SABRE Lite\n"); 737 738 return 0; 739 } 740 741 struct button_key { 742 char const *name; 743 unsigned gpnum; 744 char ident; 745 }; 746 747 static struct button_key const buttons[] = { 748 {"back", IMX_GPIO_NR(2, 2), 'B'}, 749 {"home", IMX_GPIO_NR(2, 4), 'H'}, 750 {"menu", IMX_GPIO_NR(2, 1), 'M'}, 751 {"search", IMX_GPIO_NR(2, 3), 'S'}, 752 {"volup", IMX_GPIO_NR(7, 13), 'V'}, 753 {"voldown", IMX_GPIO_NR(4, 5), 'v'}, 754 }; 755 756 /* 757 * generate a null-terminated string containing the buttons pressed 758 * returns number of keys pressed 759 */ 760 static int read_keys(char *buf) 761 { 762 int i, numpressed = 0; 763 for (i = 0; i < ARRAY_SIZE(buttons); i++) { 764 if (!gpio_get_value(buttons[i].gpnum)) 765 buf[numpressed++] = buttons[i].ident; 766 } 767 buf[numpressed] = '\0'; 768 return numpressed; 769 } 770 771 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 772 { 773 char envvalue[ARRAY_SIZE(buttons)+1]; 774 int numpressed = read_keys(envvalue); 775 setenv("keybd", envvalue); 776 return numpressed == 0; 777 } 778 779 U_BOOT_CMD( 780 kbd, 1, 1, do_kbd, 781 "Tests for keypresses, sets 'keybd' environment variable", 782 "Returns 0 (true) to shell if key is pressed." 783 ); 784 785 #ifdef CONFIG_PREBOOT 786 static char const kbd_magic_prefix[] = "key_magic"; 787 static char const kbd_command_prefix[] = "key_cmd"; 788 789 static void preboot_keys(void) 790 { 791 int numpressed; 792 char keypress[ARRAY_SIZE(buttons)+1]; 793 numpressed = read_keys(keypress); 794 if (numpressed) { 795 char *kbd_magic_keys = getenv("magic_keys"); 796 char *suffix; 797 /* 798 * loop over all magic keys 799 */ 800 for (suffix = kbd_magic_keys; *suffix; ++suffix) { 801 char *keys; 802 char magic[sizeof(kbd_magic_prefix) + 1]; 803 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); 804 keys = getenv(magic); 805 if (keys) { 806 if (!strcmp(keys, keypress)) 807 break; 808 } 809 } 810 if (*suffix) { 811 char cmd_name[sizeof(kbd_command_prefix) + 1]; 812 char *cmd; 813 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); 814 cmd = getenv(cmd_name); 815 if (cmd) { 816 setenv("preboot", cmd); 817 return; 818 } 819 } 820 } 821 } 822 #endif 823 824 #ifdef CONFIG_CMD_BMODE 825 static const struct boot_mode board_boot_modes[] = { 826 /* 4 bit bus width */ 827 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 828 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 829 {NULL, 0}, 830 }; 831 #endif 832 833 int misc_init_r(void) 834 { 835 #ifdef CONFIG_PREBOOT 836 preboot_keys(); 837 #endif 838 839 #ifdef CONFIG_CMD_BMODE 840 add_board_boot_modes(board_boot_modes); 841 #endif 842 return 0; 843 } 844