1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014, Bachmann electronic GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <malloc.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/imx-common/iomux-v3.h> 15 #include <asm/imx-common/sata.h> 16 #include <asm/imx-common/mxc_i2c.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/arch/crm_regs.h> 19 #include <asm/arch/sys_proto.h> 20 #include <mmc.h> 21 #include <fsl_esdhc.h> 22 #include <netdev.h> 23 #include <i2c.h> 24 #include <pca953x.h> 25 #include <asm/gpio.h> 26 #include <phy.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 31 32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 33 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 36 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ 40 PAD_CTL_HYS) 41 42 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \ 43 PAD_CTL_SRE_FAST) 44 45 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ 46 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) 47 48 int dram_init(void) 49 { 50 gd->ram_size = imx_ddr_size(); 51 52 return 0; 53 } 54 55 static iomux_v3_cfg_t const uart1_pads[] = { 56 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 57 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 58 }; 59 60 static void setup_iomux_uart(void) 61 { 62 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 63 } 64 65 static iomux_v3_cfg_t const enet_pads[] = { 66 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), 67 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), 68 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 69 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 70 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 71 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 72 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 }; 84 85 static void setup_iomux_enet(void) 86 { 87 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 88 } 89 90 static iomux_v3_cfg_t const ecspi1_pads[] = { 91 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL), 92 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL), 93 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 94 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 95 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 96 }; 97 98 static void setup_iomux_spi(void) 99 { 100 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 101 } 102 103 int board_spi_cs_gpio(unsigned bus, unsigned cs) 104 { 105 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1; 106 } 107 108 static iomux_v3_cfg_t const feature_pads[] = { 109 /* SD card detect */ 110 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN), 111 112 /* eMMC soldered? */ 113 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP), 114 }; 115 116 static void setup_iomux_features(void) 117 { 118 imx_iomux_v3_setup_multiple_pads(feature_pads, 119 ARRAY_SIZE(feature_pads)); 120 } 121 122 int board_early_init_f(void) 123 { 124 setup_iomux_uart(); 125 setup_iomux_spi(); 126 setup_iomux_features(); 127 128 return 0; 129 } 130 131 static iomux_v3_cfg_t const usdhc3_pads[] = { 132 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 }; 144 145 iomux_v3_cfg_t const usdhc4_pads[] = { 146 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 148 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 149 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 }; 153 154 int board_mmc_getcd(struct mmc *mmc) 155 { 156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 157 int ret; 158 159 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 160 gpio_direction_input(IMX_GPIO_NR(4, 5)); 161 ret = gpio_get_value(IMX_GPIO_NR(4, 5)); 162 } else { 163 gpio_direction_input(IMX_GPIO_NR(1, 5)); 164 ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); 165 } 166 167 return ret; 168 } 169 170 struct fsl_esdhc_cfg usdhc_cfg[2] = { 171 {USDHC3_BASE_ADDR}, 172 {USDHC4_BASE_ADDR}, 173 }; 174 175 int board_mmc_init(bd_t *bis) 176 { 177 int ret; 178 u32 index = 0; 179 180 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 181 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 182 183 usdhc_cfg[0].max_bus_width = 8; 184 usdhc_cfg[1].max_bus_width = 4; 185 186 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 187 switch (index) { 188 case 0: 189 imx_iomux_v3_setup_multiple_pads( 190 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 191 break; 192 case 1: 193 imx_iomux_v3_setup_multiple_pads( 194 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 195 break; 196 default: 197 printf("Warning: you configured more USDHC controllers" 198 "(%d) then supported by the board (%d)\n", 199 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 200 return -EINVAL; 201 } 202 203 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 204 if (ret) 205 return ret; 206 } 207 208 return 0; 209 } 210 211 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 212 213 /* I2C3 - IO expander */ 214 static struct i2c_pads_info i2c_pad_info2 = { 215 .scl = { 216 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 217 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 218 .gp = IMX_GPIO_NR(3, 17) 219 }, 220 .sda = { 221 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 222 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 223 .gp = IMX_GPIO_NR(3, 18) 224 } 225 }; 226 227 static iomux_v3_cfg_t const pwm_pad[] = { 228 MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), 229 }; 230 231 static void leds_on(void) 232 { 233 /* turn on all possible leds connected via GPIO expander */ 234 i2c_set_bus_num(2); 235 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT); 236 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0); 237 } 238 239 static void backlight_lcd_off(void) 240 { 241 unsigned gpio = IMX_GPIO_NR(2, 0); 242 gpio_direction_output(gpio, 0); 243 244 gpio = IMX_GPIO_NR(2, 3); 245 gpio_direction_output(gpio, 0); 246 } 247 248 int board_eth_init(bd_t *bis) 249 { 250 uint32_t base = IMX_FEC_BASE; 251 struct mii_dev *bus = NULL; 252 struct phy_device *phydev = NULL; 253 int ret; 254 255 setup_iomux_enet(); 256 257 bus = fec_get_miibus(base, -1); 258 if (!bus) 259 return 0; 260 261 /* scan phy 0 and 5 */ 262 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII); 263 if (!phydev) { 264 free(bus); 265 return 0; 266 } 267 268 /* depending on the phy address we can detect our board version */ 269 if (phydev->addr == 0) 270 setenv("boardver", ""); 271 else 272 setenv("boardver", "mr"); 273 274 printf("using phy at %d\n", phydev->addr); 275 ret = fec_probe(bis, -1, base, bus, phydev); 276 if (ret) { 277 printf("FEC MXC: %s:failed\n", __func__); 278 free(phydev); 279 free(bus); 280 } 281 return 0; 282 } 283 284 int board_init(void) 285 { 286 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 287 288 backlight_lcd_off(); 289 290 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 291 292 leds_on(); 293 294 /* enable ecspi3 clocks */ 295 enable_cspi_clock(1, 2); 296 297 #ifdef CONFIG_CMD_SATA 298 setup_sata(); 299 #endif 300 301 return 0; 302 } 303 304 int checkboard(void) 305 { 306 puts("Board: "CONFIG_SYS_BOARD"\n"); 307 return 0; 308 } 309 310 #ifdef CONFIG_CMD_BMODE 311 static const struct boot_mode board_boot_modes[] = { 312 /* 4 bit bus width */ 313 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 314 {NULL, 0}, 315 }; 316 #endif 317 318 int misc_init_r(void) 319 { 320 #ifdef CONFIG_CMD_BMODE 321 add_board_boot_modes(board_boot_modes); 322 #endif 323 return 0; 324 } 325