1*7254d92eSHeiko Schocher/* 2*7254d92eSHeiko Schocher * Copyright (C) 2013 Boundary Devices 3*7254d92eSHeiko Schocher * 4*7254d92eSHeiko Schocher * SPDX-License-Identifier: GPL-2.0+ 5*7254d92eSHeiko Schocher */ 6*7254d92eSHeiko Schocher/* ZQ Calibration */ 7*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 8*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 9*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 10*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 11*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 12*7254d92eSHeiko Schocher/* 13*7254d92eSHeiko Schocher * DQS gating, read delay, write delay calibration values 14*7254d92eSHeiko Schocher */ 15*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217 16*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B 17*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B 18*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C 19*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C 20*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48 21*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40 22*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E 23*7254d92eSHeiko Schocher/* read data bit delay */ 24*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 25*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 26*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 27*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 28*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 29*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 30*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 31*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 32*7254d92eSHeiko Schocher/* Complete calibration by forced measurment */ 33*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 34*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 35*7254d92eSHeiko Schocher/* in DDR3, 64-bit mode, only MMDC0 is initiated */ 36*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDPDC, 0x00020025 37*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 38*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313 39*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63 40*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 41*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 42*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 43*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 44*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDOR, 0x006B1023 45*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDASP, 0x00000027 46*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 47*7254d92eSHeiko Schocher 48*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 49*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 50*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 51*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 52*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 53*7254d92eSHeiko Schocher 54*7254d92eSHeiko Schocher/* final ddr setup */ 55*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 56*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 57*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 58*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDPDC, 0x00025565 59*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 60*7254d92eSHeiko SchocherDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 61