1 /* 2 * Aries M53 module 3 * 4 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/arch/crm_regs.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/iomux-mx53.h> 16 #include <asm/mach-imx/mx5_video.h> 17 #include <asm/spl.h> 18 #include <linux/errno.h> 19 #include <netdev.h> 20 #include <i2c.h> 21 #include <mmc.h> 22 #include <spl.h> 23 #include <fsl_esdhc.h> 24 #include <asm/gpio.h> 25 #include <usb/ehci-ci.h> 26 #include <linux/fb.h> 27 #include <ipu_pixfmt.h> 28 29 /* Special MXCFB sync flags are here. */ 30 #include "../drivers/video/mxcfb.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static uint32_t mx53_dram_size[2]; 35 36 phys_size_t get_effective_memsize(void) 37 { 38 /* 39 * WARNING: We must override get_effective_memsize() function here 40 * to report only the size of the first DRAM bank. This is to make 41 * U-Boot relocator place U-Boot into valid memory, that is, at the 42 * end of the first DRAM bank. If we did not override this function 43 * like so, U-Boot would be placed at the address of the first DRAM 44 * bank + total DRAM size - sizeof(uboot), which in the setup where 45 * each DRAM bank contains 512MiB of DRAM would result in placing 46 * U-Boot into invalid memory area close to the end of the first 47 * DRAM bank. 48 */ 49 return mx53_dram_size[0]; 50 } 51 52 int dram_init(void) 53 { 54 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); 55 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); 56 57 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; 58 59 return 0; 60 } 61 62 int dram_init_banksize(void) 63 { 64 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 65 gd->bd->bi_dram[0].size = mx53_dram_size[0]; 66 67 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 68 gd->bd->bi_dram[1].size = mx53_dram_size[1]; 69 70 return 0; 71 } 72 73 static void setup_iomux_uart(void) 74 { 75 static const iomux_v3_cfg_t uart_pads[] = { 76 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, 77 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, 78 }; 79 80 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 81 } 82 83 #ifdef CONFIG_USB_EHCI_MX5 84 int board_ehci_hcd_init(int port) 85 { 86 if (port == 0) { 87 /* USB OTG PWRON */ 88 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, 89 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); 90 gpio_direction_output(IMX_GPIO_NR(1, 4), 0); 91 92 /* USB OTG Over Current */ 93 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); 94 } else if (port == 1) { 95 /* USB Host PWRON */ 96 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, 97 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); 98 gpio_direction_output(IMX_GPIO_NR(1, 2), 0); 99 100 /* USB Host Over Current */ 101 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); 102 } 103 104 return 0; 105 } 106 #endif 107 108 static void setup_iomux_fec(void) 109 { 110 static const iomux_v3_cfg_t fec_pads[] = { 111 /* MDIO pads */ 112 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 113 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 114 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 115 116 /* FEC 0 pads */ 117 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 118 PAD_CTL_HYS | PAD_CTL_PKE), 119 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 120 PAD_CTL_HYS | PAD_CTL_PKE), 121 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 122 PAD_CTL_HYS | PAD_CTL_PKE), 123 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 124 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 125 PAD_CTL_HYS | PAD_CTL_PKE), 126 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 127 PAD_CTL_HYS | PAD_CTL_PKE), 128 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 129 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 130 131 /* FEC 1 pads */ 132 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, 133 PAD_CTL_HYS | PAD_CTL_PKE), 134 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER, 135 PAD_CTL_HYS | PAD_CTL_PKE), 136 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, 137 PAD_CTL_HYS | PAD_CTL_PKE), 138 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, 139 PAD_CTL_HYS | PAD_CTL_PKE), 140 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, 141 PAD_CTL_HYS | PAD_CTL_PKE), 142 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), 143 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, 144 PAD_CTL_HYS | PAD_CTL_PKE), 145 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), 146 }; 147 148 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 149 } 150 151 #ifdef CONFIG_FSL_ESDHC 152 struct fsl_esdhc_cfg esdhc_cfg = { 153 MMC_SDHC1_BASE_ADDR, 154 }; 155 156 int board_mmc_getcd(struct mmc *mmc) 157 { 158 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); 159 gpio_direction_input(IMX_GPIO_NR(1, 1)); 160 161 return !gpio_get_value(IMX_GPIO_NR(1, 1)); 162 } 163 164 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 165 PAD_CTL_PUS_100K_UP) 166 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 167 PAD_CTL_DSE_HIGH) 168 169 int board_mmc_init(bd_t *bis) 170 { 171 static const iomux_v3_cfg_t sd1_pads[] = { 172 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 173 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 174 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 175 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 176 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 177 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 178 MX53_PAD_EIM_DA13__GPIO3_13, 179 180 MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */ 181 }; 182 183 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 184 185 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); 186 187 /* GPIO 2_31 is SD power */ 188 gpio_direction_output(IMX_GPIO_NR(2, 31), 0); 189 190 return fsl_esdhc_initialize(bis, &esdhc_cfg); 191 } 192 #endif 193 194 #ifdef CONFIG_VIDEO 195 static struct fb_videomode const ampire_wvga = { 196 .name = "Ampire", 197 .refresh = 60, 198 .xres = 800, 199 .yres = 480, 200 .pixclock = 29851, /* picosecond (33.5 MHz) */ 201 .left_margin = 89, 202 .right_margin = 164, 203 .upper_margin = 23, 204 .lower_margin = 10, 205 .hsync_len = 10, 206 .vsync_len = 10, 207 .sync = FB_SYNC_CLK_LAT_FALL, 208 }; 209 210 int board_video_skip(void) 211 { 212 int ret; 213 ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); 214 if (ret) 215 printf("Ampire LCD cannot be configured: %d\n", ret); 216 return ret; 217 } 218 #endif 219 220 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 221 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 222 223 static void setup_iomux_i2c(void) 224 { 225 static const iomux_v3_cfg_t i2c_pads[] = { 226 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), 227 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), 228 }; 229 230 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); 231 } 232 233 static void setup_iomux_video(void) 234 { 235 static const iomux_v3_cfg_t lcd_pads[] = { 236 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, 237 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, 238 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, 239 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, 240 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, 241 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, 242 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, 243 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, 244 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, 245 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, 246 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, 247 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, 248 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, 249 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, 250 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, 251 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, 252 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, 253 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, 254 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, 255 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, 256 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, 257 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, 258 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, 259 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, 260 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, 261 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, 262 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, 263 MX53_PAD_EIM_DA15__IPU_DI1_PIN1, 264 MX53_PAD_EIM_DA11__IPU_DI1_PIN2, 265 MX53_PAD_EIM_DA12__IPU_DI1_PIN3, 266 MX53_PAD_EIM_A25__IPU_DI1_PIN12, 267 MX53_PAD_EIM_DA10__IPU_DI1_PIN15, 268 }; 269 270 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 271 } 272 273 static void setup_iomux_nand(void) 274 { 275 static const iomux_v3_cfg_t nand_pads[] = { 276 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, 277 PAD_CTL_DSE_HIGH), 278 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, 279 PAD_CTL_DSE_HIGH), 280 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, 281 PAD_CTL_DSE_HIGH), 282 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, 283 PAD_CTL_DSE_HIGH), 284 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, 285 PAD_CTL_PUS_100K_UP), 286 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, 287 PAD_CTL_PUS_100K_UP), 288 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, 289 PAD_CTL_DSE_HIGH), 290 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0, 291 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 292 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1, 293 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 294 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2, 295 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 296 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3, 297 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 298 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4, 299 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 300 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5, 301 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 302 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6, 303 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 304 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7, 305 PAD_CTL_DSE_HIGH | PAD_CTL_PKE), 306 }; 307 308 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); 309 } 310 311 static void m53_set_clock(void) 312 { 313 int ret; 314 const uint32_t ref_clk = MXC_HCLK; 315 const uint32_t dramclk = 400; 316 uint32_t cpuclk; 317 318 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, 319 PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); 320 gpio_direction_input(IMX_GPIO_NR(4, 0)); 321 322 /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ 323 cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; 324 325 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); 326 if (ret) 327 printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); 328 329 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); 330 if (ret) { 331 printf("CPU: Switch peripheral clock to %dMHz failed\n", 332 dramclk); 333 } 334 335 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); 336 if (ret) 337 printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); 338 } 339 340 static void m53_set_nand(void) 341 { 342 u32 i; 343 344 /* NAND flash is muxed on ATA pins */ 345 setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); 346 347 /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ 348 for (i = 0x4; i < 0x94; i += 0x18) { 349 clrbits_le32(WEIM_BASE_ADDR + i, 350 WEIM_GCR2_MUX16_BYP_GRANT_MASK); 351 } 352 353 mxc_set_clock(0, 33, MXC_NFC_CLK); 354 enable_nfc_clk(1); 355 } 356 357 int board_early_init_f(void) 358 { 359 setup_iomux_uart(); 360 setup_iomux_fec(); 361 setup_iomux_i2c(); 362 setup_iomux_nand(); 363 setup_iomux_video(); 364 365 m53_set_clock(); 366 367 mxc_set_sata_internal_clock(); 368 369 /* NAND clock @ 33MHz */ 370 m53_set_nand(); 371 372 return 0; 373 } 374 375 int board_init(void) 376 { 377 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 378 379 return 0; 380 } 381 382 int checkboard(void) 383 { 384 puts("Board: Aries M53EVK\n"); 385 386 return 0; 387 } 388 389 /* 390 * NAND SPL 391 */ 392 #ifdef CONFIG_SPL_BUILD 393 void spl_board_init(void) 394 { 395 setup_iomux_nand(); 396 m53_set_clock(); 397 m53_set_nand(); 398 } 399 400 u32 spl_boot_device(void) 401 { 402 return BOOT_DEVICE_NAND; 403 } 404 #endif 405