1*606576d5SStefan Roese /*
2*606576d5SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*606576d5SStefan Roese *
4*606576d5SStefan Roese * SPDX-License-Identifier: GPL-2.0+
5*606576d5SStefan Roese */
6*606576d5SStefan Roese
7*606576d5SStefan Roese #include <common.h>
8*606576d5SStefan Roese #include <miiphy.h>
9*606576d5SStefan Roese #include <netdev.h>
10*606576d5SStefan Roese #include <asm/io.h>
11*606576d5SStefan Roese #include <asm/arch/cpu.h>
12*606576d5SStefan Roese #include <asm/arch/soc.h>
13*606576d5SStefan Roese
14*606576d5SStefan Roese DECLARE_GLOBAL_DATA_PTR;
15*606576d5SStefan Roese
16*606576d5SStefan Roese /*
17*606576d5SStefan Roese * Those values and defines are taken from the Marvell U-Boot version
18*606576d5SStefan Roese * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
19*606576d5SStefan Roese */
20*606576d5SStefan Roese #define DB_88F6720_MPP0_7 0x00020020 /* SPI */
21*606576d5SStefan Roese #define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
22*606576d5SStefan Roese #define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
23*606576d5SStefan Roese #define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
24*606576d5SStefan Roese #define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
25*606576d5SStefan Roese #define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
26*606576d5SStefan Roese #define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
27*606576d5SStefan Roese #define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
28*606576d5SStefan Roese #define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
29*606576d5SStefan Roese
30*606576d5SStefan Roese #define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
31*606576d5SStefan Roese #define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
32*606576d5SStefan Roese #define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
33*606576d5SStefan Roese #define DB_88F6720_GPP_OUT_VAL_LOW 0x0
34*606576d5SStefan Roese #define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
35*606576d5SStefan Roese #define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
36*606576d5SStefan Roese #define DB_88F6720_GPP_POL_LOW 0x0
37*606576d5SStefan Roese #define DB_88F6720_GPP_POL_MID 0x0
38*606576d5SStefan Roese #define DB_88F6720_GPP_POL_HIGH 0x0
39*606576d5SStefan Roese
board_early_init_f(void)40*606576d5SStefan Roese int board_early_init_f(void)
41*606576d5SStefan Roese {
42*606576d5SStefan Roese /* Configure MPP */
43*606576d5SStefan Roese writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
44*606576d5SStefan Roese writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
45*606576d5SStefan Roese writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
46*606576d5SStefan Roese writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
47*606576d5SStefan Roese writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
48*606576d5SStefan Roese writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
49*606576d5SStefan Roese writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
50*606576d5SStefan Roese writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
51*606576d5SStefan Roese writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
52*606576d5SStefan Roese
53*606576d5SStefan Roese /* Configure GPIO */
54*606576d5SStefan Roese /* Set GPP Out value */
55*606576d5SStefan Roese writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
56*606576d5SStefan Roese writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
57*606576d5SStefan Roese writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
58*606576d5SStefan Roese
59*606576d5SStefan Roese /* Set GPP Polarity */
60*606576d5SStefan Roese writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
61*606576d5SStefan Roese writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
62*606576d5SStefan Roese writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
63*606576d5SStefan Roese
64*606576d5SStefan Roese /* Set GPP Out Enable */
65*606576d5SStefan Roese writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
66*606576d5SStefan Roese writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
67*606576d5SStefan Roese writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
68*606576d5SStefan Roese
69*606576d5SStefan Roese return 0;
70*606576d5SStefan Roese }
71*606576d5SStefan Roese
board_init(void)72*606576d5SStefan Roese int board_init(void)
73*606576d5SStefan Roese {
74*606576d5SStefan Roese /* adress of boot parameters */
75*606576d5SStefan Roese gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
76*606576d5SStefan Roese
77*606576d5SStefan Roese return 0;
78*606576d5SStefan Roese }
79*606576d5SStefan Roese
checkboard(void)80*606576d5SStefan Roese int checkboard(void)
81*606576d5SStefan Roese {
82*606576d5SStefan Roese puts("Board: Marvell DB-88F6720\n");
83*606576d5SStefan Roese
84*606576d5SStefan Roese return 0;
85*606576d5SStefan Roese }
86*606576d5SStefan Roese
board_eth_init(bd_t * bis)87*606576d5SStefan Roese int board_eth_init(bd_t *bis)
88*606576d5SStefan Roese {
89*606576d5SStefan Roese cpu_eth_init(bis); /* Built in controller(s) come first */
90*606576d5SStefan Roese return pci_eth_init(bis);
91*606576d5SStefan Roese }
92