1*c978b524SChris Zankel /* 2*c978b524SChris Zankel * Copyright (C) 2008-2013 Tensilica Inc. 3*c978b524SChris Zankel * Copyright (C) 2016 Cadence Design Systems Inc. 4*c978b524SChris Zankel * 5*c978b524SChris Zankel * SPDX-License-Identifier: GPL-2.0+ 6*c978b524SChris Zankel */ 7*c978b524SChris Zankel 8*c978b524SChris Zankel #ifndef _XTENSA_ADDRSPACE_H 9*c978b524SChris Zankel #define _XTENSA_ADDRSPACE_H 10*c978b524SChris Zankel 11*c978b524SChris Zankel #include <asm/arch/core.h> 12*c978b524SChris Zankel 13*c978b524SChris Zankel /* 14*c978b524SChris Zankel * MMU Memory Map 15*c978b524SChris Zankel * 16*c978b524SChris Zankel * noMMU and v3 MMU have identity mapped address space on reset. 17*c978b524SChris Zankel * V2 MMU: 18*c978b524SChris Zankel * IO (uncached) f0000000..ffffffff -> f000000 19*c978b524SChris Zankel * IO (cached) e0000000..efffffff -> f000000 20*c978b524SChris Zankel * MEM (uncached) d8000000..dfffffff -> 0000000 21*c978b524SChris Zankel * MEM (cached) d0000000..d7ffffff -> 0000000 22*c978b524SChris Zankel * 23*c978b524SChris Zankel * The actual location of memory and IO is the board property. 24*c978b524SChris Zankel */ 25*c978b524SChris Zankel 26*c978b524SChris Zankel #define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) 27*c978b524SChris Zankel #define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) 28*c978b524SChris Zankel #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ 29*c978b524SChris Zankel XCHAL_VECBASE_RESET_PADDR) 30*c978b524SChris Zankel 31*c978b524SChris Zankel #endif /* _XTENSA_ADDRSPACE_H */ 32