1*da3fe247SBin Meng /*
2*da3fe247SBin Meng * (C) Copyright 2009
3*da3fe247SBin Meng * Graeme Russ, <graeme.russ@gmail.com>
4*da3fe247SBin Meng *
5*da3fe247SBin Meng * (C) Copyright 2002
6*da3fe247SBin Meng * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7*da3fe247SBin Meng *
8*da3fe247SBin Meng * SPDX-License-Identifier: GPL-2.0+
9*da3fe247SBin Meng */
10*da3fe247SBin Meng
11*da3fe247SBin Meng /*
12*da3fe247SBin Meng * This file provides the interrupt handling functionality for systems
13*da3fe247SBin Meng * based on the standard PC/AT architecture using two cascaded i8259
14*da3fe247SBin Meng * Programmable Interrupt Controllers.
15*da3fe247SBin Meng */
16*da3fe247SBin Meng
17*da3fe247SBin Meng #include <common.h>
18*da3fe247SBin Meng #include <asm/io.h>
19*da3fe247SBin Meng #include <asm/i8259.h>
20*da3fe247SBin Meng #include <asm/ibmpc.h>
21*da3fe247SBin Meng #include <asm/interrupt.h>
22*da3fe247SBin Meng
i8259_init(void)23*da3fe247SBin Meng int i8259_init(void)
24*da3fe247SBin Meng {
25*da3fe247SBin Meng u8 i;
26*da3fe247SBin Meng
27*da3fe247SBin Meng /* Mask all interrupts */
28*da3fe247SBin Meng outb(0xff, MASTER_PIC + IMR);
29*da3fe247SBin Meng outb(0xff, SLAVE_PIC + IMR);
30*da3fe247SBin Meng
31*da3fe247SBin Meng /*
32*da3fe247SBin Meng * Master PIC
33*da3fe247SBin Meng * Place master PIC interrupts at INT20
34*da3fe247SBin Meng */
35*da3fe247SBin Meng outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
36*da3fe247SBin Meng outb(0x20, MASTER_PIC + ICW2);
37*da3fe247SBin Meng outb(IR2, MASTER_PIC + ICW3);
38*da3fe247SBin Meng outb(ICW4_PM, MASTER_PIC + ICW4);
39*da3fe247SBin Meng
40*da3fe247SBin Meng for (i = 0; i < 8; i++)
41*da3fe247SBin Meng outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
42*da3fe247SBin Meng
43*da3fe247SBin Meng /*
44*da3fe247SBin Meng * Slave PIC
45*da3fe247SBin Meng * Place slave PIC interrupts at INT28
46*da3fe247SBin Meng */
47*da3fe247SBin Meng outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
48*da3fe247SBin Meng outb(0x28, SLAVE_PIC + ICW2);
49*da3fe247SBin Meng outb(0x02, SLAVE_PIC + ICW3);
50*da3fe247SBin Meng outb(ICW4_PM, SLAVE_PIC + ICW4);
51*da3fe247SBin Meng
52*da3fe247SBin Meng for (i = 0; i < 8; i++)
53*da3fe247SBin Meng outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
54*da3fe247SBin Meng
55*da3fe247SBin Meng /*
56*da3fe247SBin Meng * Enable cascaded interrupts by unmasking the cascade IRQ pin of
57*da3fe247SBin Meng * the master PIC
58*da3fe247SBin Meng */
59*da3fe247SBin Meng unmask_irq(2);
60*da3fe247SBin Meng
61*da3fe247SBin Meng /* Interrupt 9 should be level triggered (SCI). The OS might do this */
62*da3fe247SBin Meng configure_irq_trigger(9, true);
63*da3fe247SBin Meng
64*da3fe247SBin Meng return 0;
65*da3fe247SBin Meng }
66*da3fe247SBin Meng
mask_irq(int irq)67*da3fe247SBin Meng void mask_irq(int irq)
68*da3fe247SBin Meng {
69*da3fe247SBin Meng int imr_port;
70*da3fe247SBin Meng
71*da3fe247SBin Meng if (irq >= SYS_NUM_IRQS)
72*da3fe247SBin Meng return;
73*da3fe247SBin Meng
74*da3fe247SBin Meng if (irq > 7)
75*da3fe247SBin Meng imr_port = SLAVE_PIC + IMR;
76*da3fe247SBin Meng else
77*da3fe247SBin Meng imr_port = MASTER_PIC + IMR;
78*da3fe247SBin Meng
79*da3fe247SBin Meng outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
80*da3fe247SBin Meng }
81*da3fe247SBin Meng
unmask_irq(int irq)82*da3fe247SBin Meng void unmask_irq(int irq)
83*da3fe247SBin Meng {
84*da3fe247SBin Meng int imr_port;
85*da3fe247SBin Meng
86*da3fe247SBin Meng if (irq >= SYS_NUM_IRQS)
87*da3fe247SBin Meng return;
88*da3fe247SBin Meng
89*da3fe247SBin Meng if (irq > 7)
90*da3fe247SBin Meng imr_port = SLAVE_PIC + IMR;
91*da3fe247SBin Meng else
92*da3fe247SBin Meng imr_port = MASTER_PIC + IMR;
93*da3fe247SBin Meng
94*da3fe247SBin Meng outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
95*da3fe247SBin Meng }
96*da3fe247SBin Meng
specific_eoi(int irq)97*da3fe247SBin Meng void specific_eoi(int irq)
98*da3fe247SBin Meng {
99*da3fe247SBin Meng if (irq >= SYS_NUM_IRQS)
100*da3fe247SBin Meng return;
101*da3fe247SBin Meng
102*da3fe247SBin Meng if (irq > 7) {
103*da3fe247SBin Meng /*
104*da3fe247SBin Meng * IRQ is on the slave - Issue a corresponding EOI to the
105*da3fe247SBin Meng * slave PIC and an EOI for IRQ2 (the cascade interrupt)
106*da3fe247SBin Meng * on the master PIC
107*da3fe247SBin Meng */
108*da3fe247SBin Meng outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
109*da3fe247SBin Meng irq = SEOI_IR2;
110*da3fe247SBin Meng }
111*da3fe247SBin Meng
112*da3fe247SBin Meng outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
113*da3fe247SBin Meng }
114*da3fe247SBin Meng
configure_irq_trigger(int int_num,bool is_level_triggered)115*da3fe247SBin Meng void configure_irq_trigger(int int_num, bool is_level_triggered)
116*da3fe247SBin Meng {
117*da3fe247SBin Meng u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
118*da3fe247SBin Meng
119*da3fe247SBin Meng debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
120*da3fe247SBin Meng if (is_level_triggered)
121*da3fe247SBin Meng int_bits |= (1 << int_num);
122*da3fe247SBin Meng else
123*da3fe247SBin Meng int_bits &= ~(1 << int_num);
124*da3fe247SBin Meng
125*da3fe247SBin Meng /* Write new values */
126*da3fe247SBin Meng debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
127*da3fe247SBin Meng outb((u8)(int_bits & 0xff), ELCR1);
128*da3fe247SBin Meng outb((u8)(int_bits >> 8), ELCR2);
129*da3fe247SBin Meng }
130