1*9f1fad1eSBin Meng /* 2*9f1fad1eSBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3*9f1fad1eSBin Meng * 4*9f1fad1eSBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*9f1fad1eSBin Meng */ 6*9f1fad1eSBin Meng 7*9f1fad1eSBin Meng /* 8*9f1fad1eSBin Meng * This library provides CMOS (inside RTC SRAM) access routines at a very 9*9f1fad1eSBin Meng * early stage when driver model is not available yet. Only read access is 10*9f1fad1eSBin Meng * provided. The 16-bit/32-bit read are compatible with driver model RTC 11*9f1fad1eSBin Meng * uclass write ops, that data is stored in little-endian mode. 12*9f1fad1eSBin Meng */ 13*9f1fad1eSBin Meng 14*9f1fad1eSBin Meng #include <common.h> 15*9f1fad1eSBin Meng #include <asm/early_cmos.h> 16*9f1fad1eSBin Meng #include <asm/io.h> 17*9f1fad1eSBin Meng cmos_read8(u8 addr)18*9f1fad1eSBin Mengu8 cmos_read8(u8 addr) 19*9f1fad1eSBin Meng { 20*9f1fad1eSBin Meng outb(addr, CMOS_IO_PORT); 21*9f1fad1eSBin Meng 22*9f1fad1eSBin Meng return inb(CMOS_IO_PORT + 1); 23*9f1fad1eSBin Meng } 24*9f1fad1eSBin Meng cmos_read16(u8 addr)25*9f1fad1eSBin Mengu16 cmos_read16(u8 addr) 26*9f1fad1eSBin Meng { 27*9f1fad1eSBin Meng u16 value = 0; 28*9f1fad1eSBin Meng u16 data; 29*9f1fad1eSBin Meng int i; 30*9f1fad1eSBin Meng 31*9f1fad1eSBin Meng for (i = 0; i < sizeof(value); i++) { 32*9f1fad1eSBin Meng data = cmos_read8(addr + i); 33*9f1fad1eSBin Meng value |= data << (i << 3); 34*9f1fad1eSBin Meng } 35*9f1fad1eSBin Meng 36*9f1fad1eSBin Meng return value; 37*9f1fad1eSBin Meng } 38*9f1fad1eSBin Meng cmos_read32(u8 addr)39*9f1fad1eSBin Mengu32 cmos_read32(u8 addr) 40*9f1fad1eSBin Meng { 41*9f1fad1eSBin Meng u32 value = 0; 42*9f1fad1eSBin Meng u32 data; 43*9f1fad1eSBin Meng int i; 44*9f1fad1eSBin Meng 45*9f1fad1eSBin Meng for (i = 0; i < sizeof(value); i++) { 46*9f1fad1eSBin Meng data = cmos_read8(addr + i); 47*9f1fad1eSBin Meng value |= data << (i << 3); 48*9f1fad1eSBin Meng } 49*9f1fad1eSBin Meng 50*9f1fad1eSBin Meng return value; 51*9f1fad1eSBin Meng } 52