1*59ec719dSBin Meng /* 2*59ec719dSBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*59ec719dSBin Meng * 4*59ec719dSBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*59ec719dSBin Meng */ 6*59ec719dSBin Meng 7*59ec719dSBin Meng #include <common.h> 8*59ec719dSBin Meng #include <asm/e820.h> 9*59ec719dSBin Meng 10*59ec719dSBin Meng DECLARE_GLOBAL_DATA_PTR; 11*59ec719dSBin Meng 12*59ec719dSBin Meng /* 13*59ec719dSBin Meng * Install a default e820 table with 4 entries as follows: 14*59ec719dSBin Meng * 15*59ec719dSBin Meng * 0x000000-0x0a0000 Useable RAM 16*59ec719dSBin Meng * 0x0a0000-0x100000 Reserved for ISA 17*59ec719dSBin Meng * 0x100000-gd->ram_size Useable RAM 18*59ec719dSBin Meng * CONFIG_PCIE_ECAM_BASE PCIe ECAM 19*59ec719dSBin Meng */ install_e820_map(unsigned max_entries,struct e820entry * entries)20*59ec719dSBin Meng__weak unsigned install_e820_map(unsigned max_entries, 21*59ec719dSBin Meng struct e820entry *entries) 22*59ec719dSBin Meng { 23*59ec719dSBin Meng entries[0].addr = 0; 24*59ec719dSBin Meng entries[0].size = ISA_START_ADDRESS; 25*59ec719dSBin Meng entries[0].type = E820_RAM; 26*59ec719dSBin Meng entries[1].addr = ISA_START_ADDRESS; 27*59ec719dSBin Meng entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; 28*59ec719dSBin Meng entries[1].type = E820_RESERVED; 29*59ec719dSBin Meng entries[2].addr = ISA_END_ADDRESS; 30*59ec719dSBin Meng entries[2].size = gd->ram_size - ISA_END_ADDRESS; 31*59ec719dSBin Meng entries[2].type = E820_RAM; 32*59ec719dSBin Meng entries[3].addr = CONFIG_PCIE_ECAM_BASE; 33*59ec719dSBin Meng entries[3].size = CONFIG_PCIE_ECAM_SIZE; 34*59ec719dSBin Meng entries[3].type = E820_RESERVED; 35*59ec719dSBin Meng 36*59ec719dSBin Meng return 4; 37*59ec719dSBin Meng } 38