1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 4fea25720SGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6fea25720SGraeme Russ */ 7fea25720SGraeme Russ 8fea25720SGraeme Russ #ifndef _U_BOOT_I386_H_ 9fea25720SGraeme Russ #define _U_BOOT_I386_H_ 1 10fea25720SGraeme Russ 11002610f6SBin Meng extern char gdt_rom[]; 12002610f6SBin Meng 13fea25720SGraeme Russ /* cpu/.../cpu.c */ 148b37c769SSimon Glass int arch_cpu_init(void); 15fea25720SGraeme Russ int x86_cpu_init_f(void); 16fea25720SGraeme Russ int cpu_init_f(void); 179e6c572fSGraeme Russ void init_gd(gd_t *id, u64 *gdt_addr); 189e6c572fSGraeme Russ void setup_gdt(gd_t *id, u64 *gdt_addr); 19002610f6SBin Meng /* 20002610f6SBin Meng * Setup FSP execution environment GDT to use the one we used in 21002610f6SBin Meng * arch/x86/cpu/start16.S and reload the segment registers. 22002610f6SBin Meng */ 23002610f6SBin Meng void setup_fsp_gdt(void); 24d653244bSGraeme Russ int init_cache(void); 25f30fc4deSGabe Black int cleanup_before_linux(void); 26fea25720SGraeme Russ 27fea25720SGraeme Russ /* cpu/.../timer.c */ 28fea25720SGraeme Russ void timer_isr(void *); 29fea25720SGraeme Russ typedef void (timer_fnc_t) (void); 30fea25720SGraeme Russ int register_timer_isr (timer_fnc_t *isr_func); 31e761ecdbSSimon Glass unsigned long get_tbclk_mhz(void); 32e761ecdbSSimon Glass void timer_set_base(uint64_t base); 33d0b6f247SSimon Glass int pcat_timer_init(void); 34fea25720SGraeme Russ 35fea25720SGraeme Russ /* cpu/.../interrupts.c */ 36fea25720SGraeme Russ int cpu_init_interrupts(void); 37fea25720SGraeme Russ 38e1ffd817SSimon Glass int cleanup_before_linux(void); 39e1ffd817SSimon Glass int x86_cleanup_before_linux(void); 40e1ffd817SSimon Glass void x86_enable_caches(void); 41e1ffd817SSimon Glass void x86_disable_caches(void); 42e1ffd817SSimon Glass int x86_init_cache(void); 43e1ffd817SSimon Glass void reset_cpu(ulong addr); 44e1ffd817SSimon Glass ulong board_get_usable_ram_top(ulong total_size); 45e1ffd817SSimon Glass void dram_init_banksize(void); 46727c1a98SSimon Glass int default_print_cpuinfo(void); 47e1ffd817SSimon Glass 48447f8b01SSimon Glass /* Set up a UART which can be used with printch(), printhex8(), etc. */ 49447f8b01SSimon Glass int setup_early_uart(void); 50447f8b01SSimon Glass 51fea25720SGraeme Russ void setup_pcat_compatibility(void); 52fea25720SGraeme Russ 53fea25720SGraeme Russ void isa_unmap_rom(u32 addr); 54fea25720SGraeme Russ u32 isa_map_rom(u32 bus_addr, int size); 55fea25720SGraeme Russ 56fea25720SGraeme Russ /* arch/x86/lib/... */ 57fea25720SGraeme Russ int video_bios_init(void); 58fea25720SGraeme Russ 59*aefaff8eSBin Meng /* arch/x86/lib/fsp/... */ 60*aefaff8eSBin Meng int x86_fsp_init(void); 61*aefaff8eSBin Meng 62f48dd6fcSGraeme Russ void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); 63f48dd6fcSGraeme Russ void board_init_f_r(void) __attribute__ ((noreturn)); 64fea25720SGraeme Russ 65afbf1404SBin Meng int arch_misc_init(void); 66afbf1404SBin Meng 672f899e03SVadim Bendebury /* Read the time stamp counter */ 68d8819f94SSimon Glass static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) 692f899e03SVadim Bendebury { 702f899e03SVadim Bendebury uint32_t high, low; 712f899e03SVadim Bendebury __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)); 722f899e03SVadim Bendebury return (((uint64_t)high) << 32) | low; 732f899e03SVadim Bendebury } 742f899e03SVadim Bendebury 752f899e03SVadim Bendebury /* board/... */ 762f899e03SVadim Bendebury void timer_set_tsc_base(uint64_t new_base); 772f899e03SVadim Bendebury uint64_t timer_get_tsc(void); 782f899e03SVadim Bendebury 7965dd74a6SSimon Glass void quick_ram_check(void); 8065dd74a6SSimon Glass 81bcb0c61eSSimon Glass int x86_init_cpus(void); 82bcb0c61eSSimon Glass 83bdc88d4eSSimon Glass #define PCI_VGA_RAM_IMAGE_START 0xc0000 84bdc88d4eSSimon Glass 85fea25720SGraeme Russ #endif /* _U_BOOT_I386_H_ */ 86