1*45b5a378SSimon Glass /* 2*45b5a378SSimon Glass * Copyright (c) 2015 Google, Inc 3*45b5a378SSimon Glass * 4*45b5a378SSimon Glass * SPDX-License-Identifier: GPL-2.0 5*45b5a378SSimon Glass * 6*45b5a378SSimon Glass * Taken from coreboot file of the same name 7*45b5a378SSimon Glass */ 8*45b5a378SSimon Glass 9*45b5a378SSimon Glass #ifndef _X86_MP_H_ 10*45b5a378SSimon Glass #define _X86_MP_H_ 11*45b5a378SSimon Glass 12*45b5a378SSimon Glass #include <asm/atomic.h> 13*45b5a378SSimon Glass 14*45b5a378SSimon Glass typedef int (*mp_callback_t)(struct udevice *cpu, void *arg); 15*45b5a378SSimon Glass 16*45b5a378SSimon Glass /* 17*45b5a378SSimon Glass * A mp_flight_record details a sequence of calls for the APs to perform 18*45b5a378SSimon Glass * along with the BSP to coordinate sequencing. Each flight record either 19*45b5a378SSimon Glass * provides a barrier for each AP before calling the callback or the APs 20*45b5a378SSimon Glass * are allowed to perform the callback without waiting. Regardless, each 21*45b5a378SSimon Glass * record has the cpus_entered field incremented for each record. When 22*45b5a378SSimon Glass * the BSP observes that the cpus_entered matches the number of APs 23*45b5a378SSimon Glass * the bsp_call is called with bsp_arg and upon returning releases the 24*45b5a378SSimon Glass * barrier allowing the APs to make further progress. 25*45b5a378SSimon Glass * 26*45b5a378SSimon Glass * Note that ap_call() and bsp_call() can be NULL. In the NULL case the 27*45b5a378SSimon Glass * callback will just not be called. 28*45b5a378SSimon Glass */ 29*45b5a378SSimon Glass struct mp_flight_record { 30*45b5a378SSimon Glass atomic_t barrier; 31*45b5a378SSimon Glass atomic_t cpus_entered; 32*45b5a378SSimon Glass mp_callback_t ap_call; 33*45b5a378SSimon Glass void *ap_arg; 34*45b5a378SSimon Glass mp_callback_t bsp_call; 35*45b5a378SSimon Glass void *bsp_arg; 36*45b5a378SSimon Glass } __attribute__((aligned(ARCH_DMA_MINALIGN))); 37*45b5a378SSimon Glass 38*45b5a378SSimon Glass #define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ 39*45b5a378SSimon Glass { \ 40*45b5a378SSimon Glass .barrier = ATOMIC_INIT(barrier_), \ 41*45b5a378SSimon Glass .cpus_entered = ATOMIC_INIT(0), \ 42*45b5a378SSimon Glass .ap_call = ap_func_, \ 43*45b5a378SSimon Glass .ap_arg = ap_arg_, \ 44*45b5a378SSimon Glass .bsp_call = bsp_func_, \ 45*45b5a378SSimon Glass .bsp_arg = bsp_arg_, \ 46*45b5a378SSimon Glass } 47*45b5a378SSimon Glass 48*45b5a378SSimon Glass #define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ 49*45b5a378SSimon Glass MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg) 50*45b5a378SSimon Glass 51*45b5a378SSimon Glass #define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ 52*45b5a378SSimon Glass MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg) 53*45b5a378SSimon Glass 54*45b5a378SSimon Glass /* 55*45b5a378SSimon Glass * The mp_params structure provides the arguments to the mp subsystem 56*45b5a378SSimon Glass * for bringing up APs. 57*45b5a378SSimon Glass * 58*45b5a378SSimon Glass * At present this is overkill for U-Boot, but it may make it easier to add 59*45b5a378SSimon Glass * SMM support. 60*45b5a378SSimon Glass */ 61*45b5a378SSimon Glass struct mp_params { 62*45b5a378SSimon Glass int num_cpus; /* Total cpus include BSP */ 63*45b5a378SSimon Glass int parallel_microcode_load; 64*45b5a378SSimon Glass const void *microcode_pointer; 65*45b5a378SSimon Glass /* Flight plan for APs and BSP */ 66*45b5a378SSimon Glass struct mp_flight_record *flight_plan; 67*45b5a378SSimon Glass int num_records; 68*45b5a378SSimon Glass }; 69*45b5a378SSimon Glass 70*45b5a378SSimon Glass /* 71*45b5a378SSimon Glass * mp_init() will set up the SIPI vector and bring up the APs according to 72*45b5a378SSimon Glass * mp_params. Each flight record will be executed according to the plan. Note 73*45b5a378SSimon Glass * that the MP infrastructure uses SMM default area without saving it. It's 74*45b5a378SSimon Glass * up to the chipset or mainboard to either e820 reserve this area or save this 75*45b5a378SSimon Glass * region prior to calling mp_init() and restoring it after mp_init returns. 76*45b5a378SSimon Glass * 77*45b5a378SSimon Glass * At the time mp_init() is called the MTRR MSRs are mirrored into APs then 78*45b5a378SSimon Glass * caching is enabled before running the flight plan. 79*45b5a378SSimon Glass * 80*45b5a378SSimon Glass * The MP init has the following properties: 81*45b5a378SSimon Glass * 1. APs are brought up in parallel. 82*45b5a378SSimon Glass * 2. The ordering of cpu number and APIC ids is not deterministic. 83*45b5a378SSimon Glass * Therefore, one cannot rely on this property or the order of devices in 84*45b5a378SSimon Glass * the device tree unless the chipset or mainboard know the APIC ids 85*45b5a378SSimon Glass * a priori. 86*45b5a378SSimon Glass * 87*45b5a378SSimon Glass * mp_init() returns < 0 on error, 0 on success. 88*45b5a378SSimon Glass */ 89*45b5a378SSimon Glass int mp_init(struct mp_params *params); 90*45b5a378SSimon Glass 91*45b5a378SSimon Glass /* Probes the CPU device */ 92*45b5a378SSimon Glass int mp_init_cpu(struct udevice *cpu, void *unused); 93*45b5a378SSimon Glass 94*45b5a378SSimon Glass #endif /* _X86_MP_H_ */ 95