145b5a378SSimon Glass /* 245b5a378SSimon Glass * Copyright (c) 2015 Google, Inc 345b5a378SSimon Glass * 445b5a378SSimon Glass * SPDX-License-Identifier: GPL-2.0 545b5a378SSimon Glass * 645b5a378SSimon Glass * Taken from coreboot file of the same name 745b5a378SSimon Glass */ 845b5a378SSimon Glass 945b5a378SSimon Glass #ifndef _X86_MP_H_ 1045b5a378SSimon Glass #define _X86_MP_H_ 1145b5a378SSimon Glass 1245b5a378SSimon Glass #include <asm/atomic.h> 1345b5a378SSimon Glass 1445b5a378SSimon Glass typedef int (*mp_callback_t)(struct udevice *cpu, void *arg); 1545b5a378SSimon Glass 1645b5a378SSimon Glass /* 1745b5a378SSimon Glass * A mp_flight_record details a sequence of calls for the APs to perform 1845b5a378SSimon Glass * along with the BSP to coordinate sequencing. Each flight record either 1945b5a378SSimon Glass * provides a barrier for each AP before calling the callback or the APs 2045b5a378SSimon Glass * are allowed to perform the callback without waiting. Regardless, each 2145b5a378SSimon Glass * record has the cpus_entered field incremented for each record. When 2245b5a378SSimon Glass * the BSP observes that the cpus_entered matches the number of APs 2345b5a378SSimon Glass * the bsp_call is called with bsp_arg and upon returning releases the 2445b5a378SSimon Glass * barrier allowing the APs to make further progress. 2545b5a378SSimon Glass * 2645b5a378SSimon Glass * Note that ap_call() and bsp_call() can be NULL. In the NULL case the 2745b5a378SSimon Glass * callback will just not be called. 2845b5a378SSimon Glass */ 2945b5a378SSimon Glass struct mp_flight_record { 3045b5a378SSimon Glass atomic_t barrier; 3145b5a378SSimon Glass atomic_t cpus_entered; 3245b5a378SSimon Glass mp_callback_t ap_call; 3345b5a378SSimon Glass void *ap_arg; 3445b5a378SSimon Glass mp_callback_t bsp_call; 3545b5a378SSimon Glass void *bsp_arg; 3645b5a378SSimon Glass } __attribute__((aligned(ARCH_DMA_MINALIGN))); 3745b5a378SSimon Glass 3845b5a378SSimon Glass #define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ 3945b5a378SSimon Glass { \ 4045b5a378SSimon Glass .barrier = ATOMIC_INIT(barrier_), \ 4145b5a378SSimon Glass .cpus_entered = ATOMIC_INIT(0), \ 4245b5a378SSimon Glass .ap_call = ap_func_, \ 4345b5a378SSimon Glass .ap_arg = ap_arg_, \ 4445b5a378SSimon Glass .bsp_call = bsp_func_, \ 4545b5a378SSimon Glass .bsp_arg = bsp_arg_, \ 4645b5a378SSimon Glass } 4745b5a378SSimon Glass 4845b5a378SSimon Glass #define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ 4945b5a378SSimon Glass MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg) 5045b5a378SSimon Glass 5145b5a378SSimon Glass #define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ 5245b5a378SSimon Glass MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg) 5345b5a378SSimon Glass 5445b5a378SSimon Glass /* 5545b5a378SSimon Glass * The mp_params structure provides the arguments to the mp subsystem 5645b5a378SSimon Glass * for bringing up APs. 5745b5a378SSimon Glass * 5845b5a378SSimon Glass * At present this is overkill for U-Boot, but it may make it easier to add 5945b5a378SSimon Glass * SMM support. 6045b5a378SSimon Glass */ 6145b5a378SSimon Glass struct mp_params { 6245b5a378SSimon Glass int parallel_microcode_load; 6345b5a378SSimon Glass const void *microcode_pointer; 6445b5a378SSimon Glass /* Flight plan for APs and BSP */ 6545b5a378SSimon Glass struct mp_flight_record *flight_plan; 6645b5a378SSimon Glass int num_records; 6745b5a378SSimon Glass }; 6845b5a378SSimon Glass 6945b5a378SSimon Glass /* 7045b5a378SSimon Glass * mp_init() will set up the SIPI vector and bring up the APs according to 7145b5a378SSimon Glass * mp_params. Each flight record will be executed according to the plan. Note 7245b5a378SSimon Glass * that the MP infrastructure uses SMM default area without saving it. It's 7345b5a378SSimon Glass * up to the chipset or mainboard to either e820 reserve this area or save this 7445b5a378SSimon Glass * region prior to calling mp_init() and restoring it after mp_init returns. 7545b5a378SSimon Glass * 7645b5a378SSimon Glass * At the time mp_init() is called the MTRR MSRs are mirrored into APs then 7745b5a378SSimon Glass * caching is enabled before running the flight plan. 7845b5a378SSimon Glass * 7945b5a378SSimon Glass * The MP init has the following properties: 8045b5a378SSimon Glass * 1. APs are brought up in parallel. 8145b5a378SSimon Glass * 2. The ordering of cpu number and APIC ids is not deterministic. 8245b5a378SSimon Glass * Therefore, one cannot rely on this property or the order of devices in 8345b5a378SSimon Glass * the device tree unless the chipset or mainboard know the APIC ids 8445b5a378SSimon Glass * a priori. 8545b5a378SSimon Glass * 8645b5a378SSimon Glass * mp_init() returns < 0 on error, 0 on success. 8745b5a378SSimon Glass */ 8845b5a378SSimon Glass int mp_init(struct mp_params *params); 8945b5a378SSimon Glass 9045b5a378SSimon Glass /* Probes the CPU device */ 9145b5a378SSimon Glass int mp_init_cpu(struct udevice *cpu, void *unused); 9245b5a378SSimon Glass 93*be059e88SSimon Glass /* Set up additional CPUs */ 94*be059e88SSimon Glass int x86_mp_init(void); 95*be059e88SSimon Glass 9645b5a378SSimon Glass #endif /* _X86_MP_H_ */ 97