1*1021af4dSSimon Glass /* 2*1021af4dSSimon Glass * Copyright (C) 2013, Intel Corporation 3*1021af4dSSimon Glass * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4*1021af4dSSimon Glass * 5*1021af4dSSimon Glass * SPDX-License-Identifier: Intel 6*1021af4dSSimon Glass */ 7*1021af4dSSimon Glass 8*1021af4dSSimon Glass #ifndef _FSP_HEADER_H_ 9*1021af4dSSimon Glass #define _FSP_HEADER_H_ 10*1021af4dSSimon Glass 11*1021af4dSSimon Glass #define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ 12*1021af4dSSimon Glass 13*1021af4dSSimon Glass struct __packed fsp_header { 14*1021af4dSSimon Glass u32 sign; /* 'FSPH' */ 15*1021af4dSSimon Glass u32 hdr_len; /* header length */ 16*1021af4dSSimon Glass u8 reserved1[3]; 17*1021af4dSSimon Glass u8 hdr_rev; /* header rev */ 18*1021af4dSSimon Glass u32 img_rev; /* image rev */ 19*1021af4dSSimon Glass char img_id[8]; /* signature string */ 20*1021af4dSSimon Glass u32 img_size; /* image size */ 21*1021af4dSSimon Glass u32 img_base; /* image base */ 22*1021af4dSSimon Glass u32 img_attr; /* image attribute */ 23*1021af4dSSimon Glass u32 cfg_region_off; /* configuration region offset */ 24*1021af4dSSimon Glass u32 cfg_region_size; /* configuration region size */ 25*1021af4dSSimon Glass u32 api_num; /* number of API entries */ 26*1021af4dSSimon Glass u32 fsp_tempram_init; /* tempram_init offset */ 27*1021af4dSSimon Glass u32 fsp_init; /* fsp_init offset */ 28*1021af4dSSimon Glass u32 fsp_notify; /* fsp_notify offset */ 29*1021af4dSSimon Glass u32 reserved2; 30*1021af4dSSimon Glass }; 31*1021af4dSSimon Glass 32*1021af4dSSimon Glass #endif 33