xref: /rk3399_rockchip-uboot/arch/x86/include/asm/fsp/fsp_bootmode.h (revision e1cc4d31f889428a4ca73120951389c756404184)
1*1021af4dSSimon Glass /*
2*1021af4dSSimon Glass  * Copyright (C) 2013, Intel Corporation
3*1021af4dSSimon Glass  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4*1021af4dSSimon Glass  *
5*1021af4dSSimon Glass  * SPDX-License-Identifier:	Intel
6*1021af4dSSimon Glass  */
7*1021af4dSSimon Glass 
8*1021af4dSSimon Glass #ifndef __FSP_BOOT_MODE_H__
9*1021af4dSSimon Glass #define __FSP_BOOT_MODE_H__
10*1021af4dSSimon Glass 
11*1021af4dSSimon Glass /* 0x21 - 0xf..f are reserved */
12*1021af4dSSimon Glass #define BOOT_FULL_CONFIG		0x00
13*1021af4dSSimon Glass #define BOOT_MINIMAL_CONFIG		0x01
14*1021af4dSSimon Glass #define BOOT_NO_CONFIG_CHANGES		0x02
15*1021af4dSSimon Glass #define BOOT_FULL_CONFIG_PLUS_DIAG	0x03
16*1021af4dSSimon Glass #define BOOT_DEFAULT_SETTINGS		0x04
17*1021af4dSSimon Glass #define BOOT_ON_S4_RESUME		0x05
18*1021af4dSSimon Glass #define BOOT_ON_S5_RESUME		0x06
19*1021af4dSSimon Glass #define BOOT_ON_S2_RESUME		0x10
20*1021af4dSSimon Glass #define BOOT_ON_S3_RESUME		0x11
21*1021af4dSSimon Glass #define BOOT_ON_FLASH_UPDATE		0x12
22*1021af4dSSimon Glass #define BOOT_IN_RECOVERY_MODE		0x20
23*1021af4dSSimon Glass 
24*1021af4dSSimon Glass #endif
25