1*50dd3da0SSimon Glass /* 2*50dd3da0SSimon Glass * Copyright (c) 2016 Google, Inc 3*50dd3da0SSimon Glass * 4*50dd3da0SSimon Glass * SPDX-License-Identifier: GPL-2.0 5*50dd3da0SSimon Glass */ 6*50dd3da0SSimon Glass 7*50dd3da0SSimon Glass #ifndef __ASM_CPU_COMMON_H 8*50dd3da0SSimon Glass #define __ASM_CPU_COMMON_H 9*50dd3da0SSimon Glass 10*50dd3da0SSimon Glass #define IA32_PERF_CTL 0x199 11*50dd3da0SSimon Glass 12*50dd3da0SSimon Glass /** 13*50dd3da0SSimon Glass * cpu_common_init() - Set up common CPU init 14*50dd3da0SSimon Glass * 15*50dd3da0SSimon Glass * This reports BIST failure, enables the LAPIC, updates microcode, enables 16*50dd3da0SSimon Glass * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA. 17*50dd3da0SSimon Glass * 18*50dd3da0SSimon Glass * @return 0 if OK, -ve on error 19*50dd3da0SSimon Glass */ 20*50dd3da0SSimon Glass int cpu_common_init(void); 21*50dd3da0SSimon Glass 22*50dd3da0SSimon Glass /** 23*50dd3da0SSimon Glass * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate 24*50dd3da0SSimon Glass * 25*50dd3da0SSimon Glass * If a change is needed, this function will do a soft reset so it takes 26*50dd3da0SSimon Glass * effect. 27*50dd3da0SSimon Glass * 28*50dd3da0SSimon Glass * Some details are available here: 29*50dd3da0SSimon Glass * http://forum.hwbot.org/showthread.php?t=76092 30*50dd3da0SSimon Glass * 31*50dd3da0SSimon Glass * @return 0 if OK, -ve on error 32*50dd3da0SSimon Glass */ 33*50dd3da0SSimon Glass int cpu_set_flex_ratio_to_tdp_nominal(void); 34*50dd3da0SSimon Glass 35*50dd3da0SSimon Glass #endif 36