1 /* 2 * Copyright (c) 2014 The Chromium OS Authors. 3 * 4 * Part of this file is adapted from coreboot 5 * src/arch/x86/include/arch/cpu.h and 6 * src/arch/x86/lib/cpu.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _ASM_CPU_H 12 #define _ASM_CPU_H 13 14 enum { 15 X86_VENDOR_INVALID = 0, 16 X86_VENDOR_INTEL, 17 X86_VENDOR_CYRIX, 18 X86_VENDOR_AMD, 19 X86_VENDOR_UMC, 20 X86_VENDOR_NEXGEN, 21 X86_VENDOR_CENTAUR, 22 X86_VENDOR_RISE, 23 X86_VENDOR_TRANSMETA, 24 X86_VENDOR_NSC, 25 X86_VENDOR_SIS, 26 X86_VENDOR_ANY = 0xfe, 27 X86_VENDOR_UNKNOWN = 0xff 28 }; 29 30 /* Global descriptor table (GDT) bits */ 31 enum { 32 GDT_4KB = 1ULL << 55, 33 GDT_32BIT = 1ULL << 54, 34 GDT_LONG = 1ULL << 53, 35 GDT_PRESENT = 1ULL << 47, 36 GDT_NOTSYS = 1ULL << 44, 37 GDT_CODE = 1ULL << 43, 38 GDT_LIMIT_LOW_SHIFT = 0, 39 GDT_LIMIT_LOW_MASK = 0xffff, 40 GDT_LIMIT_HIGH_SHIFT = 48, 41 GDT_LIMIT_HIGH_MASK = 0xf, 42 GDT_BASE_LOW_SHIFT = 16, 43 GDT_BASE_LOW_MASK = 0xffff, 44 GDT_BASE_HIGH_SHIFT = 56, 45 GDT_BASE_HIGH_MASK = 0xf, 46 }; 47 48 /* 49 * System controllers in an x86 system. We mostly need to just find these and 50 * use them on PCI. At some point these might have their own uclass. 51 */ 52 enum { 53 X86_NONE, 54 X86_SYSCON_ME, /* Intel Management Engine */ 55 }; 56 57 struct cpuid_result { 58 uint32_t eax; 59 uint32_t ebx; 60 uint32_t ecx; 61 uint32_t edx; 62 }; 63 64 /* 65 * Generic CPUID function 66 */ 67 static inline struct cpuid_result cpuid(int op) 68 { 69 struct cpuid_result result; 70 asm volatile( 71 "mov %%ebx, %%edi;" 72 "cpuid;" 73 "mov %%ebx, %%esi;" 74 "mov %%edi, %%ebx;" 75 : "=a" (result.eax), 76 "=S" (result.ebx), 77 "=c" (result.ecx), 78 "=d" (result.edx) 79 : "0" (op) 80 : "edi"); 81 return result; 82 } 83 84 /* 85 * Generic Extended CPUID function 86 */ 87 static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) 88 { 89 struct cpuid_result result; 90 asm volatile( 91 "mov %%ebx, %%edi;" 92 "cpuid;" 93 "mov %%ebx, %%esi;" 94 "mov %%edi, %%ebx;" 95 : "=a" (result.eax), 96 "=S" (result.ebx), 97 "=c" (result.ecx), 98 "=d" (result.edx) 99 : "0" (op), "2" (ecx) 100 : "edi"); 101 return result; 102 } 103 104 /* 105 * CPUID functions returning a single datum 106 */ 107 static inline unsigned int cpuid_eax(unsigned int op) 108 { 109 unsigned int eax; 110 111 __asm__("mov %%ebx, %%edi;" 112 "cpuid;" 113 "mov %%edi, %%ebx;" 114 : "=a" (eax) 115 : "0" (op) 116 : "ecx", "edx", "edi"); 117 return eax; 118 } 119 120 static inline unsigned int cpuid_ebx(unsigned int op) 121 { 122 unsigned int eax, ebx; 123 124 __asm__("mov %%ebx, %%edi;" 125 "cpuid;" 126 "mov %%ebx, %%esi;" 127 "mov %%edi, %%ebx;" 128 : "=a" (eax), "=S" (ebx) 129 : "0" (op) 130 : "ecx", "edx", "edi"); 131 return ebx; 132 } 133 134 static inline unsigned int cpuid_ecx(unsigned int op) 135 { 136 unsigned int eax, ecx; 137 138 __asm__("mov %%ebx, %%edi;" 139 "cpuid;" 140 "mov %%edi, %%ebx;" 141 : "=a" (eax), "=c" (ecx) 142 : "0" (op) 143 : "edx", "edi"); 144 return ecx; 145 } 146 147 static inline unsigned int cpuid_edx(unsigned int op) 148 { 149 unsigned int eax, edx; 150 151 __asm__("mov %%ebx, %%edi;" 152 "cpuid;" 153 "mov %%edi, %%ebx;" 154 : "=a" (eax), "=d" (edx) 155 : "0" (op) 156 : "ecx", "edi"); 157 return edx; 158 } 159 160 /* Standard macro to see if a specific flag is changeable */ 161 static inline int flag_is_changeable_p(uint32_t flag) 162 { 163 uint32_t f1, f2; 164 165 asm( 166 "pushfl\n\t" 167 "pushfl\n\t" 168 "popl %0\n\t" 169 "movl %0,%1\n\t" 170 "xorl %2,%0\n\t" 171 "pushl %0\n\t" 172 "popfl\n\t" 173 "pushfl\n\t" 174 "popl %0\n\t" 175 "popfl\n\t" 176 : "=&r" (f1), "=&r" (f2) 177 : "ir" (flag)); 178 return ((f1^f2) & flag) != 0; 179 } 180 181 static inline void mfence(void) 182 { 183 __asm__ __volatile__("mfence" : : : "memory"); 184 } 185 186 /** 187 * cpu_enable_paging_pae() - Enable PAE-paging 188 * 189 * @cr3: Value to set in cr3 (PDPT or PML4T) 190 */ 191 void cpu_enable_paging_pae(ulong cr3); 192 193 /** 194 * cpu_disable_paging_pae() - Disable paging and PAE 195 */ 196 void cpu_disable_paging_pae(void); 197 198 /** 199 * cpu_has_64bit() - Check if the CPU has 64-bit support 200 * 201 * @return 1 if this CPU supports long mode (64-bit), 0 if not 202 */ 203 int cpu_has_64bit(void); 204 205 /** 206 * cpu_vendor_name() - Get CPU vendor name 207 * 208 * @vendor: CPU vendor enumeration number 209 * 210 * @return: Address to hold the CPU vendor name string 211 */ 212 const char *cpu_vendor_name(int vendor); 213 214 #define CPU_MAX_NAME_LEN 49 215 216 /** 217 * cpu_get_name() - Get the name of the current cpu 218 * 219 * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including 220 * @return pointer to name, which will likely be a few bytes after the start 221 * of @name 222 * \0 terminator 223 */ 224 char *cpu_get_name(char *name); 225 226 /** 227 * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) 228 * 229 * The kernel is uncompressed and the 64-bit entry point is expected to be 230 * at @target. 231 * 232 * This function is used internally - see cpu_jump_to_64bit() for a more 233 * useful function. 234 * 235 * @pgtable: Address of 24KB area containing the page table 236 * @setup_base: Pointer to the setup.bin information for the kernel 237 * @target: Pointer to the start of the kernel image 238 */ 239 void cpu_call64(ulong pgtable, ulong setup_base, ulong target); 240 241 /** 242 * cpu_call32() - Jump to a 32-bit entry point 243 * 244 * @code_seg32: 32-bit code segment to use (GDT offset, e.g. 0x20) 245 * @target: Pointer to the start of the 32-bit U-Boot image/entry point 246 * @table: Pointer to start of info table to pass to U-Boot 247 */ 248 void cpu_call32(ulong code_seg32, ulong target, ulong table); 249 250 /** 251 * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel 252 * 253 * The kernel is uncompressed and the 64-bit entry point is expected to be 254 * at @target. 255 * 256 * @setup_base: Pointer to the setup.bin information for the kernel 257 * @target: Pointer to the start of the kernel image 258 */ 259 int cpu_jump_to_64bit(ulong setup_base, ulong target); 260 261 #endif 262