1adfe3b24SBin Meng /* 2adfe3b24SBin Meng * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3adfe3b24SBin Meng * 4adfe3b24SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5adfe3b24SBin Meng */ 6adfe3b24SBin Meng 7adfe3b24SBin Meng #ifndef _X86_ARCH_TNC_H_ 8adfe3b24SBin Meng #define _X86_ARCH_TNC_H_ 9adfe3b24SBin Meng 10*e5ffa4bbSBin Meng /* IGD Function Disable Register */ 11*e5ffa4bbSBin Meng #define IGD_FD 0xc4 12*e5ffa4bbSBin Meng #define FUNC_DISABLE 0x00000001 131f124ebaSBin Meng 14afbf1404SBin Meng /* Memory BAR Enable */ 15afbf1404SBin Meng #define MEM_BAR_EN 0x00000001 16adfe3b24SBin Meng 17afbf1404SBin Meng /* LPC PCI Configuration Registers */ 18afbf1404SBin Meng #define LPC_RCBA 0xf0 19afbf1404SBin Meng 20afbf1404SBin Meng /* Root Complex Register Block */ 21afbf1404SBin Meng struct tnc_rcba { 22afbf1404SBin Meng u32 rctl; 23afbf1404SBin Meng u32 esd; 24afbf1404SBin Meng u32 rsvd1[2]; 25afbf1404SBin Meng u32 hdd; 26afbf1404SBin Meng u32 rsvd2; 27afbf1404SBin Meng u32 hdba; 28afbf1404SBin Meng u32 rsvd3[3129]; 29afbf1404SBin Meng u32 d31ip; 30afbf1404SBin Meng u32 rsvd4[3]; 31afbf1404SBin Meng u32 d27ip; 32afbf1404SBin Meng u32 rsvd5; 33afbf1404SBin Meng u32 d02ip; 34afbf1404SBin Meng u32 rsvd6; 35afbf1404SBin Meng u32 d26ip; 36afbf1404SBin Meng u32 d25ip; 37afbf1404SBin Meng u32 d24ip; 38afbf1404SBin Meng u32 d23ip; 39afbf1404SBin Meng u32 d03ip; 40afbf1404SBin Meng u32 rsvd7[3]; 41afbf1404SBin Meng u16 d31ir; 42afbf1404SBin Meng u16 rsvd8[3]; 43afbf1404SBin Meng u16 d27ir; 44afbf1404SBin Meng u16 d26ir; 45afbf1404SBin Meng u16 d25ir; 46afbf1404SBin Meng u16 d24ir; 47afbf1404SBin Meng u16 d23ir; 48afbf1404SBin Meng u16 rsvd9[7]; 49afbf1404SBin Meng u16 d02ir; 50afbf1404SBin Meng u16 d03ir; 51afbf1404SBin Meng }; 52adfe3b24SBin Meng 53adfe3b24SBin Meng #endif /* _X86_ARCH_TNC_H_ */ 54