1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _QUARK_H_ 8 #define _QUARK_H_ 9 10 /* Message Bus Ports */ 11 #define MSG_PORT_MEM_ARBITER 0x00 12 #define MSG_PORT_HOST_BRIDGE 0x03 13 #define MSG_PORT_RMU 0x04 14 #define MSG_PORT_MEM_MGR 0x05 15 #define MSG_PORT_USB_AFE 0x14 16 #define MSG_PORT_PCIE_AFE 0x16 17 #define MSG_PORT_SOC_UNIT 0x31 18 19 /* Port 0x00: Memory Arbiter Message Port Registers */ 20 21 /* Enhanced Configuration Space */ 22 #define AEC_CTRL 0x00 23 24 /* Port 0x03: Host Bridge Message Port Registers */ 25 26 /* Host Miscellaneous Controls 2 */ 27 #define HMISC2 0x03 28 29 #define HMISC2_SEGE 0x00000002 30 #define HMISC2_SEGF 0x00000004 31 #define HMISC2_SEGAB 0x00000010 32 33 /* Host Memory I/O Boundary */ 34 #define HM_BOUND 0x08 35 #define HM_BOUND_LOCK 0x00000001 36 37 /* Extended Configuration Space */ 38 #define HEC_REG 0x09 39 40 /* Port 0x04: Remote Management Unit Message Port Registers */ 41 42 /* ACPI PBLK Base Address Register */ 43 #define PBLK_BA 0x70 44 45 /* Control Register */ 46 #define RMU_CTRL 0x71 47 48 /* SPI DMA Base Address Register */ 49 #define SPI_DMA_BA 0x7a 50 51 /* Thermal Sensor Register */ 52 #define TS_MODE 0xb0 53 #define TS_TEMP 0xb1 54 #define TS_TRIP 0xb2 55 56 /* Port 0x05: Memory Manager Message Port Registers */ 57 58 /* eSRAM Block Page Control */ 59 #define ESRAM_BLK_CTRL 0x82 60 #define ESRAM_BLOCK_MODE 0x10000000 61 62 /* Port 0x14: USB2 AFE Unit Port Registers */ 63 64 #define USB2_GLOBAL_PORT 0x4001 65 #define USB2_PLL1 0x7f02 66 #define USB2_PLL2 0x7f03 67 #define USB2_COMPBG 0x7f04 68 69 /* Port 0x16: PCIe AFE Unit Port Registers */ 70 71 #define PCIE_RXPICTRL0_L0 0x2080 72 #define PCIE_RXPICTRL0_L1 0x2180 73 74 /* Port 0x31: SoC Unit Port Registers */ 75 76 /* Thermal Sensor Config */ 77 #define TS_CFG1 0x31 78 #define TS_CFG2 0x32 79 #define TS_CFG3 0x33 80 #define TS_CFG4 0x34 81 82 /* PCIe Controller Config */ 83 #define PCIE_CFG 0x36 84 #define PCIE_CTLR_PRI_RST 0x00010000 85 #define PCIE_PHY_SB_RST 0x00020000 86 #define PCIE_CTLR_SB_RST 0x00040000 87 #define PCIE_PHY_LANE_RST 0x00090000 88 #define PCIE_CTLR_MAIN_RST 0x00100000 89 90 /* DRAM */ 91 #define DRAM_BASE 0x00000000 92 #define DRAM_MAX_SIZE 0x80000000 93 94 /* eSRAM */ 95 #define ESRAM_SIZE 0x80000 96 97 /* Memory BAR Enable */ 98 #define MEM_BAR_EN 0x00000001 99 100 /* I/O BAR Enable */ 101 #define IO_BAR_EN 0x80000000 102 103 /* 64KiB of RMU binary in flash */ 104 #define RMU_BINARY_SIZE 0x10000 105 106 /* PCIe Root Port Configuration Registers */ 107 108 #define PCIE_RP_CCFG 0xd0 109 #define CCFG_UPRS (1 << 14) 110 #define CCFG_UNRS (1 << 15) 111 #define CCFG_UNSD (1 << 23) 112 #define CCFG_UPSD (1 << 24) 113 114 #define PCIE_RP_MPC2 0xd4 115 #define MPC2_IPF (1 << 11) 116 117 #define PCIE_RP_MBC 0xf4 118 #define MBC_SBIC (3 << 16) 119 120 /* Legacy Bridge PCI Configuration Registers */ 121 #define LB_GBA 0x44 122 #define LB_PM1BLK 0x48 123 #define LB_GPE0BLK 0x4c 124 #define LB_ACTL 0x58 125 #define LB_PABCDRC 0x60 126 #define LB_PEFGHRC 0x64 127 #define LB_WDTBA 0x84 128 #define LB_BCE 0xd4 129 #define LB_BC 0xd8 130 #define LB_RCBA 0xf0 131 132 /* USB EHCI memory-mapped registers */ 133 #define EHCI_INSNREG01 0x94 134 135 /* USB device memory-mapped registers */ 136 #define USBD_INT_MASK 0x410 137 #define USBD_EP_INT_STS 0x414 138 #define USBD_EP_INT_MASK 0x418 139 140 #ifndef __ASSEMBLY__ 141 142 /* Root Complex Register Block */ 143 struct quark_rcba { 144 u32 rctl; 145 u32 esd; 146 u32 rsvd1[3150]; 147 u16 rmu_ir; 148 u16 d23_ir; 149 u16 core_ir; 150 u16 d20d21_ir; 151 }; 152 153 #include <asm/io.h> 154 #include <asm/pci.h> 155 156 /** 157 * qrk_pci_read_config_dword() - Read a configuration value 158 * 159 * @dev: PCI device address: bus, device and function 160 * @offset: Dword offset within the device's configuration space 161 * @valuep: Place to put the returned value 162 * 163 * Note: This routine is inlined to provide better performance on Quark 164 */ 165 static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset, 166 u32 *valuep) 167 { 168 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 169 *valuep = inl(PCI_REG_DATA); 170 } 171 172 /** 173 * qrk_pci_write_config_dword() - Write a PCI configuration value 174 * 175 * @dev: PCI device address: bus, device and function 176 * @offset: Dword offset within the device's configuration space 177 * @value: Value to write 178 * 179 * Note: This routine is inlined to provide better performance on Quark 180 */ 181 static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset, 182 u32 value) 183 { 184 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 185 outl(value, PCI_REG_DATA); 186 } 187 188 /** 189 * board_assert_perst() - Assert the PERST# pin 190 * 191 * The CPU interface to the PERST# signal on Quark is platform dependent. 192 * Board-specific codes need supply this routine to assert PCIe slot reset. 193 * 194 * The tricky part in this routine is that any APIs that may trigger PCI 195 * enumeration process are strictly forbidden, as any access to PCIe root 196 * port's configuration registers will cause system hang while it is held 197 * in reset. 198 */ 199 void board_assert_perst(void); 200 201 /** 202 * board_deassert_perst() - De-assert the PERST# pin 203 * 204 * The CPU interface to the PERST# signal on Quark is platform dependent. 205 * Board-specific codes need supply this routine to de-assert PCIe slot reset. 206 * 207 * The tricky part in this routine is that any APIs that may trigger PCI 208 * enumeration process are strictly forbidden, as any access to PCIe root 209 * port's configuration registers will cause system hang while it is held 210 * in reset. 211 */ 212 void board_deassert_perst(void); 213 214 #endif /* __ASSEMBLY__ */ 215 216 #endif /* _QUARK_H_ */ 217