1a65b25d1SBin Meng /* 2a65b25d1SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3a65b25d1SBin Meng * 4a65b25d1SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5a65b25d1SBin Meng */ 6a65b25d1SBin Meng 7a65b25d1SBin Meng #ifndef _ARCH_QEMU_H_ 8a65b25d1SBin Meng #define _ARCH_QEMU_H_ 9a65b25d1SBin Meng 10cc7debc7SBin Meng /* Programmable Attribute Map (PAM) Registers */ 11cc7debc7SBin Meng #define I440FX_PAM 0x59 12cc7debc7SBin Meng #define Q35_PAM 0x90 13cc7debc7SBin Meng #define PAM_NUM 7 14cc7debc7SBin Meng #define PAM_RW 0x33 15cc7debc7SBin Meng 16e7cd070dSBin Meng /* X-Bus Chip Select Register */ 17e7cd070dSBin Meng #define XBCS 0x4e 18e7cd070dSBin Meng #define APIC_EN (1 << 8) 19e7cd070dSBin Meng 200fcb7acfSBin Meng /* IDE Timing Register */ 210fcb7acfSBin Meng #define IDE0_TIM 0x40 220fcb7acfSBin Meng #define IDE1_TIM 0x42 23e7cd070dSBin Meng #define IDE_DECODE_EN (1 << 15) 240fcb7acfSBin Meng 259830d2ebSBin Meng /* PCIe ECAM Base Address Register */ 269830d2ebSBin Meng #define PCIEX_BAR 0x60 279830d2ebSBin Meng #define BAR_EN (1 << 0) 289830d2ebSBin Meng 29a65b25d1SBin Meng /* I/O Ports */ 30a65b25d1SBin Meng #define CMOS_ADDR_PORT 0x70 31a65b25d1SBin Meng #define CMOS_DATA_PORT 0x71 32a65b25d1SBin Meng 33a65b25d1SBin Meng #define LOW_RAM_ADDR 0x34 34a65b25d1SBin Meng #define HIGH_RAM_ADDR 0x35 35a65b25d1SBin Meng 36*a3b15a05SMiao Yan /* PM registers */ 37*a3b15a05SMiao Yan #define PMBA 0x40 38*a3b15a05SMiao Yan #define PMREGMISC 0x80 39*a3b15a05SMiao Yan #define PMIOSE (1 << 0) 40*a3b15a05SMiao Yan 41a65b25d1SBin Meng #endif /* _ARCH_QEMU_H_ */ 42