1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h 5 * 6 * Copyright (C) 2008-2009 coresystems GmbH 7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #ifndef _ASM_ARCH_PCH_H 13 #define _ASM_ARCH_PCH_H 14 15 #include <pci.h> 16 17 #define DEFAULT_GPIOBASE 0x0480 18 #define DEFAULT_PMBASE 0x0500 19 20 #define SMBUS_IO_BASE 0x0400 21 22 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) 23 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) 24 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) 25 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0) 26 #define PCH_PCIE_DEV_SLOT 28 27 28 #define PCH_DEV PCI_BDF(0, 0, 0) 29 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) 30 31 /* PCI Configuration Space (D31:F0): LPC */ 32 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) 33 34 #define PMBASE 0x40 35 #define ACPI_CNTL 0x44 36 #define BIOS_CNTL 0xDC 37 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 38 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 39 #define GPIO_ROUT 0xb8 40 41 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ 42 #define LPC_EN 0x82 /* LPC IF Enables Register */ 43 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ 44 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ 45 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ 46 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ 47 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ 48 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ 49 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ 50 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ 51 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ 52 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ 53 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ 54 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ 55 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ 56 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ 57 #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) 58 59 /* PCI Configuration Space (D31:F3): SMBus */ 60 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) 61 #define SMB_BASE 0x20 62 #define HOSTC 0x40 63 #define SMB_RCV_SLVA 0x09 64 65 /* HOSTC bits */ 66 #define I2C_EN (1 << 2) 67 #define SMB_SMI_EN (1 << 1) 68 #define HST_EN (1 << 0) 69 70 /* SMBus I/O bits. */ 71 #define SMBHSTSTAT 0x0 72 #define SMBHSTCTL 0x2 73 #define SMBHSTCMD 0x3 74 #define SMBXMITADD 0x4 75 #define SMBHSTDAT0 0x5 76 #define SMBHSTDAT1 0x6 77 #define SMBBLKDAT 0x7 78 #define SMBTRNSADD 0x9 79 #define SMBSLVDATA 0xa 80 #define SMLINK_PIN_CTL 0xe 81 #define SMBUS_PIN_CTL 0xf 82 83 #define SMBUS_TIMEOUT (10 * 1000 * 100) 84 85 86 /* Root Complex Register Block */ 87 #define DEFAULT_RCBA 0xfed1c000 88 #define RCB_REG(reg) (DEFAULT_RCBA + (reg)) 89 90 #define PCH_RCBA_BASE 0xf0 91 92 #define VCH 0x0000 /* 32bit */ 93 #define VCAP1 0x0004 /* 32bit */ 94 #define VCAP2 0x0008 /* 32bit */ 95 #define PVC 0x000c /* 16bit */ 96 #define PVS 0x000e /* 16bit */ 97 98 #define V0CAP 0x0010 /* 32bit */ 99 #define V0CTL 0x0014 /* 32bit */ 100 #define V0STS 0x001a /* 16bit */ 101 102 #define V1CAP 0x001c /* 32bit */ 103 #define V1CTL 0x0020 /* 32bit */ 104 #define V1STS 0x0026 /* 16bit */ 105 106 #define RCTCL 0x0100 /* 32bit */ 107 #define ESD 0x0104 /* 32bit */ 108 #define ULD 0x0110 /* 32bit */ 109 #define ULBA 0x0118 /* 64bit */ 110 111 #define RP1D 0x0120 /* 32bit */ 112 #define RP1BA 0x0128 /* 64bit */ 113 #define RP2D 0x0130 /* 32bit */ 114 #define RP2BA 0x0138 /* 64bit */ 115 #define RP3D 0x0140 /* 32bit */ 116 #define RP3BA 0x0148 /* 64bit */ 117 #define RP4D 0x0150 /* 32bit */ 118 #define RP4BA 0x0158 /* 64bit */ 119 #define HDD 0x0160 /* 32bit */ 120 #define HDBA 0x0168 /* 64bit */ 121 #define RP5D 0x0170 /* 32bit */ 122 #define RP5BA 0x0178 /* 64bit */ 123 #define RP6D 0x0180 /* 32bit */ 124 #define RP6BA 0x0188 /* 64bit */ 125 126 #define RPC 0x0400 /* 32bit */ 127 #define RPFN 0x0404 /* 32bit */ 128 129 #define SPI_FREQ_SWSEQ 0x3893 130 #define SPI_DESC_COMP0 0x38b0 131 #define SPI_FREQ_WR_ERA 0x38b4 132 #define SOFT_RESET_CTRL 0x38f4 133 #define SOFT_RESET_DATA 0x38f8 134 135 #define RC 0x3400 /* 32bit */ 136 #define HPTC 0x3404 /* 32bit */ 137 #define GCS 0x3410 /* 32bit */ 138 #define BUC 0x3414 /* 32bit */ 139 #define PCH_DISABLE_GBE (1 << 5) 140 #define FD 0x3418 /* 32bit */ 141 #define DISPBDF 0x3424 /* 16bit */ 142 #define FD2 0x3428 /* 32bit */ 143 #define CG 0x341c /* 32bit */ 144 145 /* ICH7 GPIOBASE */ 146 #define GPIO_USE_SEL 0x00 147 #define GP_IO_SEL 0x04 148 #define GP_LVL 0x0c 149 #define GPO_BLINK 0x18 150 #define GPI_INV 0x2c 151 #define GPIO_USE_SEL2 0x30 152 #define GP_IO_SEL2 0x34 153 #define GP_LVL2 0x38 154 #define GPIO_USE_SEL3 0x40 155 #define GP_IO_SEL3 0x44 156 #define GP_LVL3 0x48 157 #define GP_RST_SEL1 0x60 158 #define GP_RST_SEL2 0x64 159 #define GP_RST_SEL3 0x68 160 161 /* ICH7 PMBASE */ 162 #define PM1_STS 0x00 163 #define WAK_STS (1 << 15) 164 #define PCIEXPWAK_STS (1 << 14) 165 #define PRBTNOR_STS (1 << 11) 166 #define RTC_STS (1 << 10) 167 #define PWRBTN_STS (1 << 8) 168 #define GBL_STS (1 << 5) 169 #define BM_STS (1 << 4) 170 #define TMROF_STS (1 << 0) 171 #define PM1_EN 0x02 172 #define PCIEXPWAK_DIS (1 << 14) 173 #define RTC_EN (1 << 10) 174 #define PWRBTN_EN (1 << 8) 175 #define GBL_EN (1 << 5) 176 #define TMROF_EN (1 << 0) 177 #define PM1_CNT 0x04 178 #define SLP_EN (1 << 13) 179 #define SLP_TYP (7 << 10) 180 #define SLP_TYP_S0 0 181 #define SLP_TYP_S1 1 182 #define SLP_TYP_S3 5 183 #define SLP_TYP_S4 6 184 #define SLP_TYP_S5 7 185 #define GBL_RLS (1 << 2) 186 #define BM_RLD (1 << 1) 187 #define SCI_EN (1 << 0) 188 #define PM1_TMR 0x08 189 #define PROC_CNT 0x10 190 #define LV2 0x14 191 #define LV3 0x15 192 #define LV4 0x16 193 #define PM2_CNT 0x50 /* mobile only */ 194 #define GPE0_STS 0x20 195 #define PME_B0_STS (1 << 13) 196 #define PME_STS (1 << 11) 197 #define BATLOW_STS (1 << 10) 198 #define PCI_EXP_STS (1 << 9) 199 #define RI_STS (1 << 8) 200 #define SMB_WAK_STS (1 << 7) 201 #define TCOSCI_STS (1 << 6) 202 #define SWGPE_STS (1 << 2) 203 #define HOT_PLUG_STS (1 << 1) 204 #define GPE0_EN 0x28 205 #define PME_B0_EN (1 << 13) 206 #define PME_EN (1 << 11) 207 #define TCOSCI_EN (1 << 6) 208 #define SMI_EN 0x30 209 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ 210 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ 211 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ 212 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ 213 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ 214 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ 215 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ 216 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ 217 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ 218 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ 219 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ 220 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */ 221 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ 222 #define SMI_STS 0x34 223 #define ALT_GP_SMI_EN 0x38 224 #define ALT_GP_SMI_STS 0x3a 225 #define GPE_CNTL 0x42 226 #define DEVACT_STS 0x44 227 #define SS_CNT 0x50 228 #define C3_RES 0x54 229 #define TCO1_STS 0x64 230 #define DMISCI_STS (1 << 9) 231 #define TCO2_STS 0x66 232 233 /** 234 * lpc_early_init() - set up LPC serial ports and other early things 235 * 236 * @blob: Device tree blob 237 * @node: Offset of LPC node 238 * @dev: PCH PCI device containing the LPC 239 * @return 0 if OK, -ve on error 240 */ 241 int lpc_early_init(const void *blob, int node, pci_dev_t dev); 242 243 #endif 244