1*2f3f477bSSimon Glass /* 2*2f3f477bSSimon Glass * Copyright (C) 2014 Google Inc. 3*2f3f477bSSimon Glass * 4*2f3f477bSSimon Glass * This file is from coreboot soc/intel/broadwell/include/soc/spi.h 5*2f3f477bSSimon Glass * 6*2f3f477bSSimon Glass * SPDX-License-Identifier: GPL-2.0 7*2f3f477bSSimon Glass */ 8*2f3f477bSSimon Glass 9*2f3f477bSSimon Glass #ifndef _BROADWELL_SPI_H_ 10*2f3f477bSSimon Glass #define _BROADWELL_SPI_H_ 11*2f3f477bSSimon Glass 12*2f3f477bSSimon Glass /* 13*2f3f477bSSimon Glass * SPI Opcode Menu setup for SPIBAR lockdown 14*2f3f477bSSimon Glass * should support most common flash chips. 15*2f3f477bSSimon Glass */ 16*2f3f477bSSimon Glass 17*2f3f477bSSimon Glass #define SPIBAR_OFFSET 0x3800 18*2f3f477bSSimon Glass #define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x))) 19*2f3f477bSSimon Glass 20*2f3f477bSSimon Glass /* Reigsters within the SPIBAR */ 21*2f3f477bSSimon Glass #define SPIBAR_SSFC 0x91 22*2f3f477bSSimon Glass #define SPIBAR_FDOC 0xb0 23*2f3f477bSSimon Glass #define SPIBAR_FDOD 0xb4 24*2f3f477bSSimon Glass 25*2f3f477bSSimon Glass #define SPIBAR_PREOP 0x94 26*2f3f477bSSimon Glass #define SPIBAR_OPTYPE 0x96 27*2f3f477bSSimon Glass #define SPIBAR_OPMENU_LOWER 0x98 28*2f3f477bSSimon Glass #define SPIBAR_OPMENU_UPPER 0x9c 29*2f3f477bSSimon Glass 30*2f3f477bSSimon Glass #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ 31*2f3f477bSSimon Glass #define SPI_OPTYPE_0 0x01 /* Write, no address */ 32*2f3f477bSSimon Glass 33*2f3f477bSSimon Glass #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ 34*2f3f477bSSimon Glass #define SPI_OPTYPE_1 0x03 /* Write, address required */ 35*2f3f477bSSimon Glass 36*2f3f477bSSimon Glass #define SPI_OPMENU_2 0x03 /* READ: Read Data */ 37*2f3f477bSSimon Glass #define SPI_OPTYPE_2 0x02 /* Read, address required */ 38*2f3f477bSSimon Glass 39*2f3f477bSSimon Glass #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ 40*2f3f477bSSimon Glass #define SPI_OPTYPE_3 0x00 /* Read, no address */ 41*2f3f477bSSimon Glass 42*2f3f477bSSimon Glass #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ 43*2f3f477bSSimon Glass #define SPI_OPTYPE_4 0x03 /* Write, address required */ 44*2f3f477bSSimon Glass 45*2f3f477bSSimon Glass #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ 46*2f3f477bSSimon Glass #define SPI_OPTYPE_5 0x00 /* Read, no address */ 47*2f3f477bSSimon Glass 48*2f3f477bSSimon Glass #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ 49*2f3f477bSSimon Glass #define SPI_OPTYPE_6 0x03 /* Write, address required */ 50*2f3f477bSSimon Glass 51*2f3f477bSSimon Glass #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ 52*2f3f477bSSimon Glass #define SPI_OPTYPE_7 0x02 /* Read, address required */ 53*2f3f477bSSimon Glass 54*2f3f477bSSimon Glass #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ 55*2f3f477bSSimon Glass (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) 56*2f3f477bSSimon Glass #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ 57*2f3f477bSSimon Glass (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) 58*2f3f477bSSimon Glass 59*2f3f477bSSimon Glass #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ 60*2f3f477bSSimon Glass (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ 61*2f3f477bSSimon Glass (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ 62*2f3f477bSSimon Glass (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) 63*2f3f477bSSimon Glass 64*2f3f477bSSimon Glass #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ 65*2f3f477bSSimon Glass 66*2f3f477bSSimon Glass #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ 67*2f3f477bSSimon Glass #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ 68*2f3f477bSSimon Glass #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ 69*2f3f477bSSimon Glass #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ 70*2f3f477bSSimon Glass #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ 71*2f3f477bSSimon Glass #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ 72*2f3f477bSSimon Glass #define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */ 73*2f3f477bSSimon Glass #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) 74*2f3f477bSSimon Glass #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ 75*2f3f477bSSimon Glass #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ 76*2f3f477bSSimon Glass #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ 77*2f3f477bSSimon Glass #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ 78*2f3f477bSSimon Glass #define SPIBAR_FADDR 0x08 /* SPI flash address */ 79*2f3f477bSSimon Glass #define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */ 80*2f3f477bSSimon Glass #define SPIBAR_SSFS 0x90 81*2f3f477bSSimon Glass #define SPIBAR_SSFS_ERROR (1 << 3) 82*2f3f477bSSimon Glass #define SPIBAR_SSFS_DONE (1 << 2) 83*2f3f477bSSimon Glass #define SPIBAR_SSFC 0x91 84*2f3f477bSSimon Glass #define SPIBAR_SSFC_DATA (1 << 14) 85*2f3f477bSSimon Glass #define SPIBAR_SSFC_GO (1 << 1) 86*2f3f477bSSimon Glass 87*2f3f477bSSimon Glass #endif 88