1*2627c7e2SSimon Glass /* 2*2627c7e2SSimon Glass * From Coreboot soc/intel/broadwell/include/soc/pei_data.h 3*2627c7e2SSimon Glass * 4*2627c7e2SSimon Glass * Copyright (C) 2014 Google Inc. 5*2627c7e2SSimon Glass * 6*2627c7e2SSimon Glass * SPDX-License-Identifier: BSD-3-Clause 7*2627c7e2SSimon Glass */ 8*2627c7e2SSimon Glass 9*2627c7e2SSimon Glass #ifndef ASM_ARCH_PEI_DATA_H 10*2627c7e2SSimon Glass #define ASM_ARCH_PEI_DATA_H 11*2627c7e2SSimon Glass 12*2627c7e2SSimon Glass #include <linux/linkage.h> 13*2627c7e2SSimon Glass 14*2627c7e2SSimon Glass #define PEI_VERSION 22 15*2627c7e2SSimon Glass 16*2627c7e2SSimon Glass typedef void asmlinkage (*tx_byte_func)(unsigned char byte); 17*2627c7e2SSimon Glass 18*2627c7e2SSimon Glass enum board_type { 19*2627c7e2SSimon Glass BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */ 20*2627c7e2SSimon Glass BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */ 21*2627c7e2SSimon Glass BOARD_TYPE_USER1, /* SV mobile */ 22*2627c7e2SSimon Glass BOARD_TYPE_USER2, /* SV desktop */ 23*2627c7e2SSimon Glass BOARD_TYPE_USER3, /* SV server */ 24*2627c7e2SSimon Glass BOARD_TYPE_ULT, /* ULT */ 25*2627c7e2SSimon Glass BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */ 26*2627c7e2SSimon Glass BOARD_TYPE_UNKNOWN, 27*2627c7e2SSimon Glass }; 28*2627c7e2SSimon Glass 29*2627c7e2SSimon Glass #define MAX_USB2_PORTS 14 30*2627c7e2SSimon Glass #define MAX_USB3_PORTS 6 31*2627c7e2SSimon Glass #define USB_OC_PIN_SKIP 8 32*2627c7e2SSimon Glass 33*2627c7e2SSimon Glass enum usb2_port_location { 34*2627c7e2SSimon Glass USB_PORT_BACK_PANEL = 0, 35*2627c7e2SSimon Glass USB_PORT_FRONT_PANEL, 36*2627c7e2SSimon Glass USB_PORT_DOCK, 37*2627c7e2SSimon Glass USB_PORT_MINI_PCIE, 38*2627c7e2SSimon Glass USB_PORT_FLEX, 39*2627c7e2SSimon Glass USB_PORT_INTERNAL, 40*2627c7e2SSimon Glass USB_PORT_SKIP, 41*2627c7e2SSimon Glass USB_PORT_NGFF_DEVICE_DOWN, 42*2627c7e2SSimon Glass }; 43*2627c7e2SSimon Glass 44*2627c7e2SSimon Glass struct usb2_port_setting { 45*2627c7e2SSimon Glass /* 46*2627c7e2SSimon Glass * Usb Port Length: 47*2627c7e2SSimon Glass * [16:4] = length in inches in octal format 48*2627c7e2SSimon Glass * [3:0] = decimal point 49*2627c7e2SSimon Glass */ 50*2627c7e2SSimon Glass uint16_t length; 51*2627c7e2SSimon Glass uint8_t enable; 52*2627c7e2SSimon Glass uint8_t oc_pin; 53*2627c7e2SSimon Glass uint8_t location; 54*2627c7e2SSimon Glass } __packed; 55*2627c7e2SSimon Glass 56*2627c7e2SSimon Glass struct usb3_port_setting { 57*2627c7e2SSimon Glass uint8_t enable; 58*2627c7e2SSimon Glass uint8_t oc_pin; 59*2627c7e2SSimon Glass /* 60*2627c7e2SSimon Glass * Set to 0 if trace length is > 5 inches 61*2627c7e2SSimon Glass * Set to 1 if trace length is <= 5 inches 62*2627c7e2SSimon Glass */ 63*2627c7e2SSimon Glass uint8_t fixed_eq; 64*2627c7e2SSimon Glass } __packed; 65*2627c7e2SSimon Glass 66*2627c7e2SSimon Glass 67*2627c7e2SSimon Glass struct pei_data { 68*2627c7e2SSimon Glass uint32_t pei_version; 69*2627c7e2SSimon Glass 70*2627c7e2SSimon Glass enum board_type board_type; 71*2627c7e2SSimon Glass int boot_mode; 72*2627c7e2SSimon Glass int ec_present; 73*2627c7e2SSimon Glass int usbdebug; 74*2627c7e2SSimon Glass 75*2627c7e2SSimon Glass /* Base addresses */ 76*2627c7e2SSimon Glass uint32_t pciexbar; 77*2627c7e2SSimon Glass uint16_t smbusbar; 78*2627c7e2SSimon Glass uint32_t xhcibar; 79*2627c7e2SSimon Glass uint32_t ehcibar; 80*2627c7e2SSimon Glass uint32_t gttbar; 81*2627c7e2SSimon Glass uint32_t rcba; 82*2627c7e2SSimon Glass uint32_t pmbase; 83*2627c7e2SSimon Glass uint32_t gpiobase; 84*2627c7e2SSimon Glass uint32_t temp_mmio_base; 85*2627c7e2SSimon Glass uint32_t tseg_size; 86*2627c7e2SSimon Glass 87*2627c7e2SSimon Glass /* 88*2627c7e2SSimon Glass * 0 = leave channel enabled 89*2627c7e2SSimon Glass * 1 = disable dimm 0 on channel 90*2627c7e2SSimon Glass * 2 = disable dimm 1 on channel 91*2627c7e2SSimon Glass * 3 = disable dimm 0+1 on channel 92*2627c7e2SSimon Glass */ 93*2627c7e2SSimon Glass int dimm_channel0_disabled; 94*2627c7e2SSimon Glass int dimm_channel1_disabled; 95*2627c7e2SSimon Glass /* Set to 0 for memory down */ 96*2627c7e2SSimon Glass uint8_t spd_addresses[4]; 97*2627c7e2SSimon Glass /* Enable 2x Refresh Mode */ 98*2627c7e2SSimon Glass int ddr_refresh_2x; 99*2627c7e2SSimon Glass /* DQ pins are interleaved on board */ 100*2627c7e2SSimon Glass int dq_pins_interleaved; 101*2627c7e2SSimon Glass /* Limit DDR3 frequency */ 102*2627c7e2SSimon Glass int max_ddr3_freq; 103*2627c7e2SSimon Glass /* Disable self refresh */ 104*2627c7e2SSimon Glass int disable_self_refresh; 105*2627c7e2SSimon Glass /* Disable cmd power/CKEPD */ 106*2627c7e2SSimon Glass int disable_cmd_pwr; 107*2627c7e2SSimon Glass 108*2627c7e2SSimon Glass /* USB port configuration */ 109*2627c7e2SSimon Glass struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; 110*2627c7e2SSimon Glass struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; 111*2627c7e2SSimon Glass 112*2627c7e2SSimon Glass /* 113*2627c7e2SSimon Glass * USB3 board specific PHY tuning 114*2627c7e2SSimon Glass */ 115*2627c7e2SSimon Glass 116*2627c7e2SSimon Glass /* Valid range: 0x69 - 0x80 */ 117*2627c7e2SSimon Glass uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS]; 118*2627c7e2SSimon Glass /* Valid range: 0x80 - 0x9c */ 119*2627c7e2SSimon Glass uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS]; 120*2627c7e2SSimon Glass /* Valid range: 0x39 - 0x80 */ 121*2627c7e2SSimon Glass uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS]; 122*2627c7e2SSimon Glass /* Valid range: 0x3d - 0x4a */ 123*2627c7e2SSimon Glass uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS]; 124*2627c7e2SSimon Glass 125*2627c7e2SSimon Glass /* Console output function */ 126*2627c7e2SSimon Glass tx_byte_func tx_byte; 127*2627c7e2SSimon Glass 128*2627c7e2SSimon Glass /* 129*2627c7e2SSimon Glass * DIMM SPD data for memory down configurations 130*2627c7e2SSimon Glass * [CHANNEL][SLOT][SPD] 131*2627c7e2SSimon Glass */ 132*2627c7e2SSimon Glass uint8_t spd_data[2][2][512]; 133*2627c7e2SSimon Glass 134*2627c7e2SSimon Glass /* 135*2627c7e2SSimon Glass * LPDDR3 DQ byte map 136*2627c7e2SSimon Glass * [CHANNEL][ITERATION][2] 137*2627c7e2SSimon Glass * 138*2627c7e2SSimon Glass * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) 139*2627c7e2SSimon Glass * DQByteMap[0] - ClkDQByteMap: 140*2627c7e2SSimon Glass * - If clock is per rank, program to [0xFF, 0xFF] 141*2627c7e2SSimon Glass * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] 142*2627c7e2SSimon Glass * - If clock is shared by 2 ranks but does not go to all bytes, 143*2627c7e2SSimon Glass * Entry[i] defines which DQ bytes Group i services 144*2627c7e2SSimon Glass * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB 145*2627c7e2SSimon Glass * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB 146*2627c7e2SSimon Glass * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB 147*2627c7e2SSimon Glass * For DDR, DQByteMap[3:1] = [0xFF, 0] 148*2627c7e2SSimon Glass * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] 149*2627c7e2SSimon Glass * since we have 1 CTL / rank 150*2627c7e2SSimon Glass * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] 151*2627c7e2SSimon Glass * since we have 1 CA Vref 152*2627c7e2SSimon Glass */ 153*2627c7e2SSimon Glass uint8_t dq_map[2][6][2]; 154*2627c7e2SSimon Glass 155*2627c7e2SSimon Glass /* 156*2627c7e2SSimon Glass * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins 157*2627c7e2SSimon Glass * [CHANNEL][MAX_BYTES] 158*2627c7e2SSimon Glass */ 159*2627c7e2SSimon Glass uint8_t dqs_map[2][8]; 160*2627c7e2SSimon Glass 161*2627c7e2SSimon Glass /* Data read from flash and passed into MRC */ 162*2627c7e2SSimon Glass const void *saved_data; 163*2627c7e2SSimon Glass int saved_data_size; 164*2627c7e2SSimon Glass 165*2627c7e2SSimon Glass /* Disable use of saved data (can be set by mainboard) */ 166*2627c7e2SSimon Glass int disable_saved_data; 167*2627c7e2SSimon Glass 168*2627c7e2SSimon Glass /* Data from MRC that should be saved to flash */ 169*2627c7e2SSimon Glass void *data_to_save; 170*2627c7e2SSimon Glass int data_to_save_size; 171*2627c7e2SSimon Glass struct pei_memory_info meminfo; 172*2627c7e2SSimon Glass } __packed; 173*2627c7e2SSimon Glass 174*2627c7e2SSimon Glass void mainboard_fill_pei_data(struct pei_data *pei_data); 175*2627c7e2SSimon Glass void broadwell_fill_pei_data(struct pei_data *pei_data); 176*2627c7e2SSimon Glass 177*2627c7e2SSimon Glass #endif 178