1*08cb7420SSimon Glass /* 2*08cb7420SSimon Glass * From coreboot soc/intel/broadwell/include/soc/lpc.h 3*08cb7420SSimon Glass * 4*08cb7420SSimon Glass * Copyright (C) 2016 Google Inc. 5*08cb7420SSimon Glass * 6*08cb7420SSimon Glass * SPDX-License-Identifier: GPL-2.0 7*08cb7420SSimon Glass */ 8*08cb7420SSimon Glass 9*08cb7420SSimon Glass #ifndef _ASM_ARCH_LPC_H 10*08cb7420SSimon Glass #define _ASM_ARCH_LPC_H 11*08cb7420SSimon Glass 12*08cb7420SSimon Glass #define GEN_PMCON_1 0xa0 13*08cb7420SSimon Glass #define SMI_LOCK (1 << 4) 14*08cb7420SSimon Glass #define GEN_PMCON_2 0xa2 15*08cb7420SSimon Glass #define SYSTEM_RESET_STS (1 << 4) 16*08cb7420SSimon Glass #define THERMTRIP_STS (1 << 3) 17*08cb7420SSimon Glass #define SYSPWR_FLR (1 << 1) 18*08cb7420SSimon Glass #define PWROK_FLR (1 << 0) 19*08cb7420SSimon Glass #define GEN_PMCON_3 0xa4 20*08cb7420SSimon Glass #define SUS_PWR_FLR (1 << 14) 21*08cb7420SSimon Glass #define GEN_RST_STS (1 << 9) 22*08cb7420SSimon Glass #define RTC_BATTERY_DEAD (1 << 2) 23*08cb7420SSimon Glass #define PWR_FLR (1 << 1) 24*08cb7420SSimon Glass #define SLEEP_AFTER_POWER_FAIL (1 << 0) 25*08cb7420SSimon Glass #define GEN_PMCON_LOCK 0xa6 26*08cb7420SSimon Glass #define SLP_STR_POL_LOCK (1 << 2) 27*08cb7420SSimon Glass #define ACPI_BASE_LOCK (1 << 1) 28*08cb7420SSimon Glass #define PMIR 0xac 29*08cb7420SSimon Glass #define PMIR_CF9LOCK (1 << 31) 30*08cb7420SSimon Glass #define PMIR_CF9GR (1 << 20) 31*08cb7420SSimon Glass 32*08cb7420SSimon Glass #endif 33