1*b24f5c4fSSimon Glass /* 2*b24f5c4fSSimon Glass * Copyright (c) 2016 Google, Inc 3*b24f5c4fSSimon Glass * 4*b24f5c4fSSimon Glass * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h 5*b24f5c4fSSimon Glass * 6*b24f5c4fSSimon Glass * SPDX-License-Identifier: GPL-2.0 7*b24f5c4fSSimon Glass */ 8*b24f5c4fSSimon Glass 9*b24f5c4fSSimon Glass #ifndef __ASM_ARCH_GPIO 10*b24f5c4fSSimon Glass #define __ASM_ARCH_GPIO 11*b24f5c4fSSimon Glass 12*b24f5c4fSSimon Glass #define GPIO_PER_BANK 32 13*b24f5c4fSSimon Glass #define GPIO_BANKS 3 14*b24f5c4fSSimon Glass 15*b24f5c4fSSimon Glass struct broadwell_bank_platdata { 16*b24f5c4fSSimon Glass uint16_t base_addr; 17*b24f5c4fSSimon Glass const char *bank_name; 18*b24f5c4fSSimon Glass int bank; 19*b24f5c4fSSimon Glass }; 20*b24f5c4fSSimon Glass 21*b24f5c4fSSimon Glass /* PCH-LP GPIOBASE Registers */ 22*b24f5c4fSSimon Glass struct pch_lp_gpio_regs { 23*b24f5c4fSSimon Glass u32 own[GPIO_BANKS]; 24*b24f5c4fSSimon Glass u32 reserved0; 25*b24f5c4fSSimon Glass 26*b24f5c4fSSimon Glass u16 pirq_to_ioxapic; 27*b24f5c4fSSimon Glass u16 reserved1[3]; 28*b24f5c4fSSimon Glass u32 blink; 29*b24f5c4fSSimon Glass u32 ser_blink; 30*b24f5c4fSSimon Glass 31*b24f5c4fSSimon Glass u32 ser_blink_cmdsts; 32*b24f5c4fSSimon Glass u32 ser_blink_data; 33*b24f5c4fSSimon Glass u16 gpi_nmi_en; 34*b24f5c4fSSimon Glass u16 gpi_nmi_sts; 35*b24f5c4fSSimon Glass u32 reserved2; 36*b24f5c4fSSimon Glass 37*b24f5c4fSSimon Glass u32 gpi_route[GPIO_BANKS]; 38*b24f5c4fSSimon Glass u32 reserved3; 39*b24f5c4fSSimon Glass 40*b24f5c4fSSimon Glass u32 reserved4[4]; 41*b24f5c4fSSimon Glass 42*b24f5c4fSSimon Glass u32 alt_gpi_smi_sts; 43*b24f5c4fSSimon Glass u32 alt_gpi_smi_en; 44*b24f5c4fSSimon Glass u32 reserved5[2]; 45*b24f5c4fSSimon Glass 46*b24f5c4fSSimon Glass u32 rst_sel[GPIO_BANKS]; 47*b24f5c4fSSimon Glass u32 reserved6; 48*b24f5c4fSSimon Glass 49*b24f5c4fSSimon Glass u32 reserved9[3]; 50*b24f5c4fSSimon Glass u32 gpio_gc; 51*b24f5c4fSSimon Glass 52*b24f5c4fSSimon Glass u32 gpi_is[GPIO_BANKS]; 53*b24f5c4fSSimon Glass u32 reserved10; 54*b24f5c4fSSimon Glass 55*b24f5c4fSSimon Glass u32 gpi_ie[GPIO_BANKS]; 56*b24f5c4fSSimon Glass u32 reserved11; 57*b24f5c4fSSimon Glass 58*b24f5c4fSSimon Glass u32 reserved12[24]; 59*b24f5c4fSSimon Glass 60*b24f5c4fSSimon Glass struct { 61*b24f5c4fSSimon Glass u32 conf_a; 62*b24f5c4fSSimon Glass u32 conf_b; 63*b24f5c4fSSimon Glass } config[GPIO_BANKS * GPIO_PER_BANK]; 64*b24f5c4fSSimon Glass }; 65*b24f5c4fSSimon Glass check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90); 66*b24f5c4fSSimon Glass check_member(pch_lp_gpio_regs, config[0], 0x100); 67*b24f5c4fSSimon Glass 68*b24f5c4fSSimon Glass enum { 69*b24f5c4fSSimon Glass CONFA_MODE_SHIFT = 0, 70*b24f5c4fSSimon Glass CONFA_MODE_GPIO = 1 << CONFA_MODE_SHIFT, 71*b24f5c4fSSimon Glass 72*b24f5c4fSSimon Glass CONFA_DIR_SHIFT = 2, 73*b24f5c4fSSimon Glass CONFA_DIR_INPUT = 1 << CONFA_DIR_SHIFT, 74*b24f5c4fSSimon Glass 75*b24f5c4fSSimon Glass CONFA_INVERT_SHIFT = 3, 76*b24f5c4fSSimon Glass CONFA_INVERT = 1 << CONFA_INVERT_SHIFT, 77*b24f5c4fSSimon Glass 78*b24f5c4fSSimon Glass CONFA_TRIGGER_SHIFT = 4, 79*b24f5c4fSSimon Glass CONFA_TRIGGER_LEVEL = 1 << CONFA_TRIGGER_SHIFT, 80*b24f5c4fSSimon Glass 81*b24f5c4fSSimon Glass CONFA_LEVEL_SHIFT = 30, 82*b24f5c4fSSimon Glass CONFA_LEVEL_HIGH = 1UL << CONFA_LEVEL_SHIFT, 83*b24f5c4fSSimon Glass 84*b24f5c4fSSimon Glass CONFA_OUTPUT_SHIFT = 31, 85*b24f5c4fSSimon Glass CONFA_OUTPUT_HIGH = 1UL << CONFA_OUTPUT_SHIFT, 86*b24f5c4fSSimon Glass 87*b24f5c4fSSimon Glass CONFB_SENSE_SHIFT = 2, 88*b24f5c4fSSimon Glass CONFB_SENSE_DISABLE = 1 << CONFB_SENSE_SHIFT, 89*b24f5c4fSSimon Glass }; 90*b24f5c4fSSimon Glass 91*b24f5c4fSSimon Glass #endif 92