1*42f8ebfdSBin Meng /* 2*42f8ebfdSBin Meng * Copyright (C) 2013 Google Inc. 3*42f8ebfdSBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*42f8ebfdSBin Meng * 5*42f8ebfdSBin Meng * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h 6*42f8ebfdSBin Meng * 7*42f8ebfdSBin Meng * SPDX-License-Identifier: GPL-2.0+ 8*42f8ebfdSBin Meng */ 9*42f8ebfdSBin Meng 10*42f8ebfdSBin Meng #ifndef _BAYTRAIL_IRQ_H_ 11*42f8ebfdSBin Meng #define _BAYTRAIL_IRQ_H_ 12*42f8ebfdSBin Meng 13*42f8ebfdSBin Meng #define PIRQA_APIC_IRQ 16 14*42f8ebfdSBin Meng #define PIRQB_APIC_IRQ 17 15*42f8ebfdSBin Meng #define PIRQC_APIC_IRQ 18 16*42f8ebfdSBin Meng #define PIRQD_APIC_IRQ 19 17*42f8ebfdSBin Meng #define PIRQE_APIC_IRQ 20 18*42f8ebfdSBin Meng #define PIRQF_APIC_IRQ 21 19*42f8ebfdSBin Meng #define PIRQG_APIC_IRQ 22 20*42f8ebfdSBin Meng #define PIRQH_APIC_IRQ 23 21*42f8ebfdSBin Meng 22*42f8ebfdSBin Meng /* The below IRQs are for when devices are in ACPI mode */ 23*42f8ebfdSBin Meng #define LPE_DMA0_IRQ 24 24*42f8ebfdSBin Meng #define LPE_DMA1_IRQ 25 25*42f8ebfdSBin Meng #define LPE_SSP0_IRQ 26 26*42f8ebfdSBin Meng #define LPE_SSP1_IRQ 27 27*42f8ebfdSBin Meng #define LPE_SSP2_IRQ 28 28*42f8ebfdSBin Meng #define LPE_IPC2HOST_IRQ 29 29*42f8ebfdSBin Meng #define LPSS_I2C1_IRQ 32 30*42f8ebfdSBin Meng #define LPSS_I2C2_IRQ 33 31*42f8ebfdSBin Meng #define LPSS_I2C3_IRQ 34 32*42f8ebfdSBin Meng #define LPSS_I2C4_IRQ 35 33*42f8ebfdSBin Meng #define LPSS_I2C5_IRQ 36 34*42f8ebfdSBin Meng #define LPSS_I2C6_IRQ 37 35*42f8ebfdSBin Meng #define LPSS_I2C7_IRQ 38 36*42f8ebfdSBin Meng #define LPSS_HSUART1_IRQ 39 37*42f8ebfdSBin Meng #define LPSS_HSUART2_IRQ 40 38*42f8ebfdSBin Meng #define LPSS_SPI_IRQ 41 39*42f8ebfdSBin Meng #define LPSS_DMA1_IRQ 42 40*42f8ebfdSBin Meng #define LPSS_DMA2_IRQ 43 41*42f8ebfdSBin Meng #define SCC_EMMC_IRQ 44 42*42f8ebfdSBin Meng #define SCC_SDIO_IRQ 46 43*42f8ebfdSBin Meng #define SCC_SD_IRQ 47 44*42f8ebfdSBin Meng #define GPIO_NC_IRQ 48 45*42f8ebfdSBin Meng #define GPIO_SC_IRQ 49 46*42f8ebfdSBin Meng #define GPIO_SUS_IRQ 50 47*42f8ebfdSBin Meng /* GPIO direct / dedicated IRQs */ 48*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_0 51 49*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_1 52 50*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_2 53 51*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_3 54 52*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_4 55 53*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_5 56 54*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_6 57 55*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_7 58 56*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_8 59 57*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_9 60 58*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_10 61 59*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_11 62 60*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_12 63 61*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_13 64 62*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_14 65 63*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_15 66 64*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_0 67 65*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_1 68 66*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_2 69 67*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_3 70 68*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_4 71 69*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_5 72 70*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_6 73 71*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_7 74 72*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_8 75 73*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_9 76 74*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_10 77 75*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_11 78 76*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_12 79 77*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_13 80 78*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_14 81 79*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_15 82 80*42f8ebfdSBin Meng /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */ 81*42f8ebfdSBin Meng #define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot 82*42f8ebfdSBin Meng #define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot 83*42f8ebfdSBin Meng #define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) 84*42f8ebfdSBin Meng #define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) 85*42f8ebfdSBin Meng 86*42f8ebfdSBin Meng #endif /* _BAYTRAIL_IRQ_H_ */ 87