1*42f8ebfdSBin Meng /* 2*42f8ebfdSBin Meng * Copyright (C) 2013 Google Inc. 3*42f8ebfdSBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*42f8ebfdSBin Meng * 5*42f8ebfdSBin Meng * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h 6*42f8ebfdSBin Meng * 7*42f8ebfdSBin Meng * SPDX-License-Identifier: GPL-2.0+ 8*42f8ebfdSBin Meng */ 9*42f8ebfdSBin Meng 10*42f8ebfdSBin Meng #ifndef _DEVICE_H_ 11*42f8ebfdSBin Meng #define _DEVICE_H_ 12*42f8ebfdSBin Meng 13*42f8ebfdSBin Meng /* 14*42f8ebfdSBin Meng * Internal PCI device numbers within the SoC. 15*42f8ebfdSBin Meng * 16*42f8ebfdSBin Meng * Note it must start with 0x_ prefix, as the device number macro will be 17*42f8ebfdSBin Meng * included in the ACPI ASL files (see irq_helper.h and irq_route.h). 18*42f8ebfdSBin Meng */ 19*42f8ebfdSBin Meng 20*42f8ebfdSBin Meng /* SoC transaction router */ 21*42f8ebfdSBin Meng #define SOC_DEV 0x00 22*42f8ebfdSBin Meng 23*42f8ebfdSBin Meng /* Graphics and Display */ 24*42f8ebfdSBin Meng #define GFX_DEV 0x02 25*42f8ebfdSBin Meng 26*42f8ebfdSBin Meng /* MIPI */ 27*42f8ebfdSBin Meng #define MIPI_DEV 0x03 28*42f8ebfdSBin Meng 29*42f8ebfdSBin Meng /* EMMC Port */ 30*42f8ebfdSBin Meng #define EMMC_DEV 0x10 31*42f8ebfdSBin Meng 32*42f8ebfdSBin Meng /* SDIO Port */ 33*42f8ebfdSBin Meng #define SDIO_DEV 0x11 34*42f8ebfdSBin Meng 35*42f8ebfdSBin Meng /* SD Port */ 36*42f8ebfdSBin Meng #define SD_DEV 0x12 37*42f8ebfdSBin Meng 38*42f8ebfdSBin Meng /* SATA */ 39*42f8ebfdSBin Meng #define SATA_DEV 0x13 40*42f8ebfdSBin Meng 41*42f8ebfdSBin Meng /* xHCI */ 42*42f8ebfdSBin Meng #define XHCI_DEV 0x14 43*42f8ebfdSBin Meng 44*42f8ebfdSBin Meng /* LPE Audio */ 45*42f8ebfdSBin Meng #define LPE_DEV 0x15 46*42f8ebfdSBin Meng 47*42f8ebfdSBin Meng /* OTG */ 48*42f8ebfdSBin Meng #define OTG_DEV 0x16 49*42f8ebfdSBin Meng 50*42f8ebfdSBin Meng /* MMC45 Port */ 51*42f8ebfdSBin Meng #define MMC45_DEV 0x17 52*42f8ebfdSBin Meng 53*42f8ebfdSBin Meng /* Serial IO 1 */ 54*42f8ebfdSBin Meng #define SIO1_DEV 0x18 55*42f8ebfdSBin Meng 56*42f8ebfdSBin Meng /* Trusted Execution Engine */ 57*42f8ebfdSBin Meng #define TXE_DEV 0x1a 58*42f8ebfdSBin Meng 59*42f8ebfdSBin Meng /* HD Audio */ 60*42f8ebfdSBin Meng #define HDA_DEV 0x1b 61*42f8ebfdSBin Meng 62*42f8ebfdSBin Meng /* PCIe Ports */ 63*42f8ebfdSBin Meng #define PCIE_DEV 0x1c 64*42f8ebfdSBin Meng 65*42f8ebfdSBin Meng /* EHCI */ 66*42f8ebfdSBin Meng #define EHCI_DEV 0x1d 67*42f8ebfdSBin Meng 68*42f8ebfdSBin Meng /* Serial IO 2 */ 69*42f8ebfdSBin Meng #define SIO2_DEV 0x1e 70*42f8ebfdSBin Meng 71*42f8ebfdSBin Meng /* Platform Controller Unit */ 72*42f8ebfdSBin Meng #define PCU_DEV 0x1f 73*42f8ebfdSBin Meng 74*42f8ebfdSBin Meng #endif /* _DEVICE_H_ */ 75