1*42f8ebfdSBin Meng/* 2*42f8ebfdSBin Meng * Copyright (C) 2007-2009 coresystems GmbH 3*42f8ebfdSBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*42f8ebfdSBin Meng * 5*42f8ebfdSBin Meng * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl 6*42f8ebfdSBin Meng * 7*42f8ebfdSBin Meng * SPDX-License-Identifier: GPL-2.0+ 8*42f8ebfdSBin Meng */ 9*42f8ebfdSBin Meng 10*42f8ebfdSBin Meng/* EHCI Controller 0:1d.0 */ 11*42f8ebfdSBin Meng 12*42f8ebfdSBin MengDevice (EHC1) 13*42f8ebfdSBin Meng{ 14*42f8ebfdSBin Meng Name(_ADR, 0x001d0000) 15*42f8ebfdSBin Meng 16*42f8ebfdSBin Meng /* Power Resources for Wake */ 17*42f8ebfdSBin Meng Name(_PRW, Package() { 13, 4 }) 18*42f8ebfdSBin Meng 19*42f8ebfdSBin Meng /* Highest D state in S3 state */ 20*42f8ebfdSBin Meng Name(_S3D, 2) 21*42f8ebfdSBin Meng 22*42f8ebfdSBin Meng /* Highest D state in S4 state */ 23*42f8ebfdSBin Meng Name(_S4D, 2) 24*42f8ebfdSBin Meng 25*42f8ebfdSBin Meng Device (HUB7) 26*42f8ebfdSBin Meng { 27*42f8ebfdSBin Meng Name(_ADR, 0x00000000) 28*42f8ebfdSBin Meng 29*42f8ebfdSBin Meng Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */ 30*42f8ebfdSBin Meng Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */ 31*42f8ebfdSBin Meng Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */ 32*42f8ebfdSBin Meng Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */ 33*42f8ebfdSBin Meng } 34*42f8ebfdSBin Meng} 35