1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "serial.dtsi" 14/include/ "rtc.dtsi" 15/include/ "tsc_timer.dtsi" 16 17/ { 18 model = "Intel Minnowboard Max"; 19 compatible = "intel,minnowmax", "intel,baytrail"; 20 21 aliases { 22 serial0 = &serial; 23 spi0 = &spi; 24 }; 25 26 config { 27 silent_console = <0>; 28 }; 29 30 pch_pinctrl { 31 compatible = "intel,x86-pinctrl"; 32 reg = <0 0>; 33 34 /* GPIO E0 */ 35 soc_gpio_s5_0@0 { 36 gpio-offset = <0x80 0>; 37 pad-offset = <0x1d0>; 38 mode-gpio; 39 output-value = <0>; 40 direction = <PIN_OUTPUT>; 41 }; 42 43 /* GPIO E1 */ 44 soc_gpio_s5_1@0 { 45 gpio-offset = <0x80 1>; 46 pad-offset = <0x210>; 47 mode-gpio; 48 output-value = <0>; 49 direction = <PIN_OUTPUT>; 50 }; 51 52 /* GPIO E2 */ 53 soc_gpio_s5_2@0 { 54 gpio-offset = <0x80 2>; 55 pad-offset = <0x1e0>; 56 mode-gpio; 57 output-value = <0>; 58 direction = <PIN_OUTPUT>; 59 }; 60 61 pin_usb_host_en0@0 { 62 gpio-offset = <0x80 8>; 63 pad-offset = <0x260>; 64 mode-gpio; 65 output-value = <1>; 66 direction = <PIN_OUTPUT>; 67 }; 68 69 pin_usb_host_en1@0 { 70 gpio-offset = <0x80 9>; 71 pad-offset = <0x250>; 72 mode-gpio; 73 output-value = <1>; 74 direction = <PIN_OUTPUT>; 75 }; 76 }; 77 78 chosen { 79 stdout-path = "/serial"; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu@0 { 87 device_type = "cpu"; 88 compatible = "intel,baytrail-cpu"; 89 reg = <0>; 90 intel,apic-id = <0>; 91 }; 92 93 cpu@1 { 94 device_type = "cpu"; 95 compatible = "intel,baytrail-cpu"; 96 reg = <1>; 97 intel,apic-id = <4>; 98 }; 99 100 }; 101 102 pci { 103 compatible = "intel,pci-baytrail", "pci-x86"; 104 #address-cells = <3>; 105 #size-cells = <2>; 106 u-boot,dm-pre-reloc; 107 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 108 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 109 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 110 111 pch@1f,0 { 112 reg = <0x0000f800 0 0 0 0>; 113 compatible = "pci8086,0f1c", "intel,pch9"; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 117 irq-router { 118 compatible = "intel,irq-router"; 119 intel,pirq-config = "ibase"; 120 intel,ibase-offset = <0x50>; 121 intel,actl-addr = <0>; 122 intel,pirq-link = <8 8>; 123 intel,pirq-mask = <0xdee0>; 124 intel,pirq-routing = < 125 /* BayTrail PCI devices */ 126 PCI_BDF(0, 2, 0) INTA PIRQA 127 PCI_BDF(0, 3, 0) INTA PIRQA 128 PCI_BDF(0, 16, 0) INTA PIRQA 129 PCI_BDF(0, 17, 0) INTA PIRQA 130 PCI_BDF(0, 18, 0) INTA PIRQA 131 PCI_BDF(0, 19, 0) INTA PIRQA 132 PCI_BDF(0, 20, 0) INTA PIRQA 133 PCI_BDF(0, 21, 0) INTA PIRQA 134 PCI_BDF(0, 22, 0) INTA PIRQA 135 PCI_BDF(0, 23, 0) INTA PIRQA 136 PCI_BDF(0, 24, 0) INTA PIRQA 137 PCI_BDF(0, 24, 1) INTC PIRQC 138 PCI_BDF(0, 24, 2) INTD PIRQD 139 PCI_BDF(0, 24, 3) INTB PIRQB 140 PCI_BDF(0, 24, 4) INTA PIRQA 141 PCI_BDF(0, 24, 5) INTC PIRQC 142 PCI_BDF(0, 24, 6) INTD PIRQD 143 PCI_BDF(0, 24, 7) INTB PIRQB 144 PCI_BDF(0, 26, 0) INTA PIRQA 145 PCI_BDF(0, 27, 0) INTA PIRQA 146 PCI_BDF(0, 28, 0) INTA PIRQA 147 PCI_BDF(0, 28, 1) INTB PIRQB 148 PCI_BDF(0, 28, 2) INTC PIRQC 149 PCI_BDF(0, 28, 3) INTD PIRQD 150 PCI_BDF(0, 29, 0) INTA PIRQA 151 PCI_BDF(0, 30, 0) INTA PIRQA 152 PCI_BDF(0, 30, 1) INTD PIRQD 153 PCI_BDF(0, 30, 2) INTB PIRQB 154 PCI_BDF(0, 30, 3) INTC PIRQC 155 PCI_BDF(0, 30, 4) INTD PIRQD 156 PCI_BDF(0, 30, 5) INTB PIRQB 157 PCI_BDF(0, 31, 3) INTB PIRQB 158 159 /* 160 * PCIe root ports downstream 161 * interrupts 162 */ 163 PCI_BDF(1, 0, 0) INTA PIRQA 164 PCI_BDF(1, 0, 0) INTB PIRQB 165 PCI_BDF(1, 0, 0) INTC PIRQC 166 PCI_BDF(1, 0, 0) INTD PIRQD 167 PCI_BDF(2, 0, 0) INTA PIRQB 168 PCI_BDF(2, 0, 0) INTB PIRQC 169 PCI_BDF(2, 0, 0) INTC PIRQD 170 PCI_BDF(2, 0, 0) INTD PIRQA 171 PCI_BDF(3, 0, 0) INTA PIRQC 172 PCI_BDF(3, 0, 0) INTB PIRQD 173 PCI_BDF(3, 0, 0) INTC PIRQA 174 PCI_BDF(3, 0, 0) INTD PIRQB 175 PCI_BDF(4, 0, 0) INTA PIRQD 176 PCI_BDF(4, 0, 0) INTB PIRQA 177 PCI_BDF(4, 0, 0) INTC PIRQB 178 PCI_BDF(4, 0, 0) INTD PIRQC 179 >; 180 }; 181 182 spi: spi { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "intel,ich9-spi"; 186 spi-flash@0 { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 reg = <0>; 190 compatible = "stmicro,n25q064a", 191 "spi-flash"; 192 memory-map = <0xff800000 0x00800000>; 193 rw-mrc-cache { 194 label = "rw-mrc-cache"; 195 reg = <0x006f0000 0x00010000>; 196 }; 197 }; 198 }; 199 200 gpioa { 201 compatible = "intel,ich6-gpio"; 202 u-boot,dm-pre-reloc; 203 reg = <0 0x20>; 204 bank-name = "A"; 205 }; 206 207 gpiob { 208 compatible = "intel,ich6-gpio"; 209 u-boot,dm-pre-reloc; 210 reg = <0x20 0x20>; 211 bank-name = "B"; 212 }; 213 214 gpioc { 215 compatible = "intel,ich6-gpio"; 216 u-boot,dm-pre-reloc; 217 reg = <0x40 0x20>; 218 bank-name = "C"; 219 }; 220 221 gpiod { 222 compatible = "intel,ich6-gpio"; 223 u-boot,dm-pre-reloc; 224 reg = <0x60 0x20>; 225 bank-name = "D"; 226 }; 227 228 gpioe { 229 compatible = "intel,ich6-gpio"; 230 u-boot,dm-pre-reloc; 231 reg = <0x80 0x20>; 232 bank-name = "E"; 233 }; 234 235 gpiof { 236 compatible = "intel,ich6-gpio"; 237 u-boot,dm-pre-reloc; 238 reg = <0xA0 0x20>; 239 bank-name = "F"; 240 }; 241 }; 242 }; 243 244 fsp { 245 compatible = "intel,baytrail-fsp"; 246 fsp,mrc-init-tseg-size = <0>; 247 fsp,mrc-init-mmio-size = <0x800>; 248 fsp,mrc-init-spd-addr1 = <0xa0>; 249 fsp,mrc-init-spd-addr2 = <0xa2>; 250 fsp,emmc-boot-mode = <1>; 251 fsp,enable-sdio; 252 fsp,enable-sdcard; 253 fsp,enable-hsuart1; 254 fsp,enable-spi; 255 fsp,enable-sata; 256 fsp,sata-mode = <1>; 257 fsp,enable-lpe; 258 fsp,lpss-sio-enable-pci-mode; 259 fsp,enable-dma0; 260 fsp,enable-dma1; 261 fsp,enable-i2c0; 262 fsp,enable-i2c1; 263 fsp,enable-i2c2; 264 fsp,enable-i2c3; 265 fsp,enable-i2c4; 266 fsp,enable-i2c5; 267 fsp,enable-i2c6; 268 fsp,enable-pwm0; 269 fsp,enable-pwm1; 270 fsp,igd-dvmt50-pre-alloc = <2>; 271 fsp,aperture-size = <2>; 272 fsp,gtt-size = <2>; 273 fsp,serial-debug-port-address = <0x3f8>; 274 fsp,serial-debug-port-type = <1>; 275 fsp,scc-enable-pci-mode; 276 fsp,os-selection = <4>; 277 fsp,emmc45-ddr50-enabled; 278 fsp,emmc45-retune-timer-value = <8>; 279 fsp,enable-igd; 280 fsp,enable-memory-down; 281 fsp,memory-down-params { 282 compatible = "intel,baytrail-fsp-mdp"; 283 fsp,dram-speed = <1>; 284 fsp,dram-type = <1>; 285 fsp,dimm-0-enable; 286 fsp,dimm-width = <1>; 287 fsp,dimm-density = <2>; 288 fsp,dimm-bus-width = <3>; 289 fsp,dimm-sides = <0>; 290 fsp,dimm-tcl = <0xb>; 291 fsp,dimm-trpt-rcd = <0xb>; 292 fsp,dimm-twr = <0xc>; 293 fsp,dimm-twtr = <6>; 294 fsp,dimm-trrd = <6>; 295 fsp,dimm-trtp = <6>; 296 fsp,dimm-tfaw = <0x14>; 297 }; 298 }; 299 300 microcode { 301 update@0 { 302#include "microcode/m0130673325.dtsi" 303 }; 304 update@1 { 305#include "microcode/m0130679907.dtsi" 306 }; 307 }; 308 309}; 310