1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <malloc.h> 10 #include <asm/io.h> 11 #include <asm/pci.h> 12 #include <asm/post.h> 13 #include <asm/processor.h> 14 #include <asm/pirq_routing.h> 15 #include <asm/arch/device.h> 16 #include <asm/arch/tnc.h> 17 #include <asm/arch/irq.h> 18 19 static struct irq_routing_table *pirq_routing_table; 20 21 bool pirq_check_irq_routed(int link, u8 irq) 22 { 23 u8 pirq; 24 25 pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link)); 26 pirq &= 0xf; 27 28 /* IRQ# 0/1/2/8/13 are reserved */ 29 if (pirq < 3 || pirq == 8 || pirq == 13) 30 return false; 31 32 return pirq == irq ? true : false; 33 } 34 35 int pirq_translate_link(int link) 36 { 37 return LINK_V2N(link); 38 } 39 40 void pirq_assign_irq(int link, u8 irq) 41 { 42 /* IRQ# 0/1/2/8/13 are reserved */ 43 if (irq < 3 || irq == 8 || irq == 13) 44 return; 45 46 x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq); 47 } 48 49 static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus, 50 u8 device, u8 func, u8 pin, u8 pirq) 51 { 52 struct irq_info *slot = *slotp; 53 54 slot->bus = bus; 55 slot->devfn = (device << 3) | func; 56 slot->irq[pin - 1].link = LINK_N2V(pirq); 57 slot->irq[pin - 1].bitmap = PIRQ_BITMAP; 58 (*entries)++; 59 (*slotp)++; 60 } 61 62 /* PCIe port downstream INTx swizzle */ 63 static inline u8 pin_swizzle(u8 pin, int port) 64 { 65 return (pin + port) % 4; 66 } 67 68 __weak int board_fill_irq_info(struct irq_info *slot) 69 { 70 return 0; 71 } 72 73 static int create_pirq_routing_table(void) 74 { 75 struct irq_routing_table *rt; 76 struct irq_info *slot; 77 int irq_entries = 0; 78 pci_dev_t tcf_bdf; 79 u8 tcf_bus, bus; 80 int i; 81 82 rt = malloc(sizeof(struct irq_routing_table)); 83 if (!rt) 84 return -ENOMEM; 85 memset((char *)rt, 0, sizeof(struct irq_routing_table)); 86 87 /* Populate the PIRQ table fields */ 88 rt->signature = PIRQ_SIGNATURE; 89 rt->version = PIRQ_VERSION; 90 rt->rtr_bus = 0; 91 rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC; 92 rt->rtr_vendor = PCI_VENDOR_ID_INTEL; 93 rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; 94 95 slot = rt->slots; 96 97 /* 98 * Now fill in the irq_info entries in the PIRQ table 99 * 100 * We start from internal TunnelCreek PCI devices first, then 101 * followed by all the 4 PCIe ports downstream devices, including 102 * the Queensbay platform Topcliff chipset devices. 103 */ 104 fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV, 105 TNC_IGD_FUNC, INTA, PIRQE); 106 fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV, 107 TNC_SDVO_FUNC, INTA, PIRQF); 108 fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV, 109 TNC_HDA_FUNC, INTA, PIRQG); 110 fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV, 111 TNC_PCIE0_FUNC, INTA, PIRQE); 112 fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV, 113 TNC_PCIE1_FUNC, INTA, PIRQF); 114 fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV, 115 TNC_PCIE2_FUNC, INTA, PIRQG); 116 fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV, 117 TNC_PCIE3_FUNC, INTA, PIRQH); 118 119 /* Check which PCIe port the Topcliff chipset is connected to */ 120 tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0); 121 tcf_bus = PCI_BUS(tcf_bdf); 122 for (i = 0; i < 4; i++) { 123 bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0), 124 PCI_SECONDARY_BUS); 125 if (bus == tcf_bus) 126 break; 127 } 128 129 /* Fill in the Topcliff chipset devices' irq info */ 130 if (i < 4) { 131 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV, 132 TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i)); 133 134 tcf_bus++; 135 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0, 136 TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i)); 137 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0, 138 TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i)); 139 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, 140 TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i)); 141 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, 142 TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i)); 143 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, 144 TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i)); 145 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, 146 TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i)); 147 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, 148 TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i)); 149 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4, 150 TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i)); 151 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4, 152 TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i)); 153 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6, 154 TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i)); 155 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, 156 TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i)); 157 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, 158 TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i)); 159 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, 160 TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i)); 161 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, 162 TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i)); 163 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, 164 TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i)); 165 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, 166 TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i)); 167 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, 168 TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i)); 169 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, 170 TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i)); 171 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, 172 TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i)); 173 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, 174 TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i)); 175 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, 176 TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i)); 177 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, 178 TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i)); 179 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, 180 TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i)); 181 fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, 182 TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i)); 183 } 184 185 /* Call board-specific routine to fill in add-in card's irq info */ 186 irq_entries += board_fill_irq_info(slot); 187 188 rt->size = irq_entries * sizeof(struct irq_info) + 32; 189 190 pirq_routing_table = rt; 191 192 return 0; 193 } 194 195 void pirq_init(void) 196 { 197 struct tnc_rcba *rcba; 198 u32 base; 199 200 base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); 201 base &= ~MEM_BAR_EN; 202 rcba = (struct tnc_rcba *)base; 203 204 /* Make sure all internal PCI devices are using INTA */ 205 writel(INTA, &rcba->d02ip); 206 writel(INTA, &rcba->d03ip); 207 writel(INTA, &rcba->d27ip); 208 writel(INTA, &rcba->d31ip); 209 writel(INTA, &rcba->d23ip); 210 writel(INTA, &rcba->d24ip); 211 writel(INTA, &rcba->d25ip); 212 writel(INTA, &rcba->d26ip); 213 214 /* 215 * Route TunnelCreek PCI device interrupt pin to PIRQ 216 * 217 * Since PCIe downstream ports received INTx are routed to PIRQ 218 * A/B/C/D directly and not configurable, we route internal PCI 219 * device's INTx to PIRQ E/F/G/H. 220 */ 221 writew(PIRQE, &rcba->d02ir); 222 writew(PIRQF, &rcba->d03ir); 223 writew(PIRQG, &rcba->d27ir); 224 writew(PIRQH, &rcba->d31ir); 225 writew(PIRQE, &rcba->d23ir); 226 writew(PIRQF, &rcba->d24ir); 227 writew(PIRQG, &rcba->d25ir); 228 writew(PIRQH, &rcba->d26ir); 229 230 if (create_pirq_routing_table()) { 231 debug("Failed to create pirq routing table\n"); 232 } else { 233 /* Route PIRQ */ 234 pirq_route_irqs(pirq_routing_table->slots, 235 get_irq_slot_count(pirq_routing_table)); 236 } 237 } 238 239 u32 write_pirq_routing_table(u32 addr) 240 { 241 return copy_pirq_routing_table(addr, pirq_routing_table); 242 } 243