1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <asm/io.h> 10 #include <asm/irq.h> 11 #include <asm/pci.h> 12 #include <asm/post.h> 13 #include <asm/processor.h> 14 #include <asm/arch/device.h> 15 #include <asm/arch/msg_port.h> 16 #include <asm/arch/quark.h> 17 18 static struct pci_device_id mmc_supported[] = { 19 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 20 }; 21 22 /* 23 * TODO: 24 * 25 * This whole routine should be removed until we fully convert the ICH SPI 26 * driver to DM and make use of DT to pass the bios control register offset 27 */ 28 static void unprotect_spi_flash(void) 29 { 30 u32 bc; 31 32 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); 33 bc |= 0x1; /* unprotect the flash */ 34 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); 35 } 36 37 static void quark_setup_bars(void) 38 { 39 /* GPIO - D31:F0:R44h */ 40 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 41 CONFIG_GPIO_BASE | IO_BAR_EN); 42 43 /* ACPI PM1 Block - D31:F0:R48h */ 44 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 45 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 46 47 /* GPE0 - D31:F0:R4Ch */ 48 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 49 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 50 51 /* WDT - D31:F0:R84h */ 52 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 53 CONFIG_WDT_BASE | IO_BAR_EN); 54 55 /* RCBA - D31:F0:RF0h */ 56 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 57 CONFIG_RCBA_BASE | MEM_BAR_EN); 58 59 /* ACPI P Block - Msg Port 04:R70h */ 60 msg_port_write(MSG_PORT_RMU, PBLK_BA, 61 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 62 63 /* SPI DMA - Msg Port 04:R7Ah */ 64 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 65 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 66 67 /* PCIe ECAM */ 68 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 69 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 70 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 71 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 72 } 73 74 static void quark_pcie_early_init(void) 75 { 76 /* 77 * Step1: Assert PCIe signal PERST# 78 * 79 * The CPU interface to the PERST# signal is platform dependent. 80 * Call the board-specific codes to perform this task. 81 */ 82 board_assert_perst(); 83 84 /* Step2: PHY common lane reset */ 85 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST); 86 /* wait 1 ms for PHY common lane reset */ 87 mdelay(1); 88 89 /* Step3: PHY sideband interface reset and controller main reset */ 90 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, 91 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 92 /* wait 80ms for PLL to lock */ 93 mdelay(80); 94 95 /* Step4: Controller sideband interface reset */ 96 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST); 97 /* wait 20ms for controller sideband interface reset */ 98 mdelay(20); 99 100 /* Step5: De-assert PERST# */ 101 board_deassert_perst(); 102 103 /* Step6: Controller primary interface reset */ 104 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST); 105 106 /* Mixer Load Lane 0 */ 107 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, 108 (1 << 6) | (1 << 7)); 109 110 /* Mixer Load Lane 1 */ 111 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, 112 (1 << 6) | (1 << 7)); 113 } 114 115 static void quark_usb_early_init(void) 116 { 117 /* The sequence below comes from Quark firmware writer guide */ 118 119 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, 120 1 << 1, (1 << 6) | (1 << 7)); 121 122 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG, 123 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10)); 124 125 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 126 127 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1); 128 129 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1, 130 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6); 131 132 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 133 134 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24); 135 } 136 137 static void quark_enable_legacy_seg(void) 138 { 139 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2, 140 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 141 } 142 143 int arch_cpu_init(void) 144 { 145 int ret; 146 147 post_code(POST_CPU_INIT); 148 #ifdef CONFIG_SYS_X86_TSC_TIMER 149 timer_set_base(rdtsc()); 150 #endif 151 152 ret = x86_cpu_init_f(); 153 if (ret) 154 return ret; 155 156 /* 157 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 158 * which need be initialized with suggested values 159 */ 160 quark_setup_bars(); 161 162 /* 163 * Initialize PCIe controller 164 * 165 * Quark SoC holds the PCIe controller in reset following a power on. 166 * U-Boot needs to release the PCIe controller from reset. The PCIe 167 * controller (D23:F0/F1) will not be visible in PCI configuration 168 * space and any access to its PCI configuration registers will cause 169 * system hang while it is held in reset. 170 */ 171 quark_pcie_early_init(); 172 173 /* Initialize USB2 PHY */ 174 quark_usb_early_init(); 175 176 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 177 quark_enable_legacy_seg(); 178 179 unprotect_spi_flash(); 180 181 return 0; 182 } 183 184 int print_cpuinfo(void) 185 { 186 post_code(POST_CPU_INFO); 187 return default_print_cpuinfo(); 188 } 189 190 void reset_cpu(ulong addr) 191 { 192 /* cold reset */ 193 x86_full_reset(); 194 } 195 196 static void quark_pcie_init(void) 197 { 198 u32 val; 199 200 /* PCIe upstream non-posted & posted request size */ 201 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 202 CCFG_UPRS | CCFG_UNRS); 203 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 204 CCFG_UPRS | CCFG_UNRS); 205 206 /* PCIe packet fast transmit mode (IPF) */ 207 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 208 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 209 210 /* PCIe message bus idle counter (SBIC) */ 211 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 212 val |= MBC_SBIC; 213 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 214 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 215 val |= MBC_SBIC; 216 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 217 } 218 219 static void quark_usb_init(void) 220 { 221 u32 bar; 222 223 /* Change USB EHCI packet buffer OUT/IN threshold */ 224 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 225 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 226 227 /* Disable USB device interrupts */ 228 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 229 writel(0x7f, bar + USBD_INT_MASK); 230 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 231 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 232 } 233 234 int arch_early_init_r(void) 235 { 236 quark_pcie_init(); 237 238 quark_usb_init(); 239 240 return 0; 241 } 242 243 int cpu_mmc_init(bd_t *bis) 244 { 245 return pci_mmc_init("Quark SDHCI", mmc_supported, 246 ARRAY_SIZE(mmc_supported)); 247 } 248 249 void cpu_irq_init(void) 250 { 251 struct quark_rcba *rcba; 252 u32 base; 253 254 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 255 base &= ~MEM_BAR_EN; 256 rcba = (struct quark_rcba *)base; 257 258 /* 259 * Route Quark PCI device interrupt pin to PIRQ 260 * 261 * Route device#23's INTA/B/C/D to PIRQA/B/C/D 262 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H 263 */ 264 writew(PIRQC, &rcba->rmu_ir); 265 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), 266 &rcba->d23_ir); 267 writew(PIRQD, &rcba->core_ir); 268 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), 269 &rcba->d20d21_ir); 270 } 271 272 int arch_misc_init(void) 273 { 274 return pirq_init(); 275 } 276 277 void board_final_cleanup(void) 278 { 279 struct quark_rcba *rcba; 280 u32 base, val; 281 282 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 283 base &= ~MEM_BAR_EN; 284 rcba = (struct quark_rcba *)base; 285 286 /* Initialize 'Component ID' to zero */ 287 val = readl(&rcba->esd); 288 val &= ~0xff0000; 289 writel(val, &rcba->esd); 290 291 return; 292 } 293