1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <asm/io.h> 10 #include <asm/irq.h> 11 #include <asm/pci.h> 12 #include <asm/post.h> 13 #include <asm/processor.h> 14 #include <asm/arch/device.h> 15 #include <asm/arch/msg_port.h> 16 #include <asm/arch/quark.h> 17 18 static struct pci_device_id mmc_supported[] = { 19 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 20 }; 21 22 /* 23 * TODO: 24 * 25 * This whole routine should be removed until we fully convert the ICH SPI 26 * driver to DM and make use of DT to pass the bios control register offset 27 */ 28 static void unprotect_spi_flash(void) 29 { 30 u32 bc; 31 32 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); 33 bc |= 0x1; /* unprotect the flash */ 34 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); 35 } 36 37 static void quark_setup_bars(void) 38 { 39 /* GPIO - D31:F0:R44h */ 40 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 41 CONFIG_GPIO_BASE | IO_BAR_EN); 42 43 /* ACPI PM1 Block - D31:F0:R48h */ 44 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 45 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 46 47 /* GPE0 - D31:F0:R4Ch */ 48 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 49 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 50 51 /* WDT - D31:F0:R84h */ 52 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 53 CONFIG_WDT_BASE | IO_BAR_EN); 54 55 /* RCBA - D31:F0:RF0h */ 56 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 57 CONFIG_RCBA_BASE | MEM_BAR_EN); 58 59 /* ACPI P Block - Msg Port 04:R70h */ 60 msg_port_write(MSG_PORT_RMU, PBLK_BA, 61 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 62 63 /* SPI DMA - Msg Port 04:R7Ah */ 64 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 65 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 66 67 /* PCIe ECAM */ 68 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 69 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 70 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 71 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 72 } 73 74 static void quark_pcie_early_init(void) 75 { 76 /* 77 * Step1: Assert PCIe signal PERST# 78 * 79 * The CPU interface to the PERST# signal is platform dependent. 80 * Call the board-specific codes to perform this task. 81 */ 82 board_assert_perst(); 83 84 /* Step2: PHY common lane reset */ 85 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST); 86 /* wait 1 ms for PHY common lane reset */ 87 mdelay(1); 88 89 /* Step3: PHY sideband interface reset and controller main reset */ 90 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, 91 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 92 /* wait 80ms for PLL to lock */ 93 mdelay(80); 94 95 /* Step4: Controller sideband interface reset */ 96 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST); 97 /* wait 20ms for controller sideband interface reset */ 98 mdelay(20); 99 100 /* Step5: De-assert PERST# */ 101 board_deassert_perst(); 102 103 /* Step6: Controller primary interface reset */ 104 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST); 105 106 /* Mixer Load Lane 0 */ 107 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, 108 (1 << 6) | (1 << 7)); 109 110 /* Mixer Load Lane 1 */ 111 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, 112 (1 << 6) | (1 << 7)); 113 } 114 115 static void quark_usb_early_init(void) 116 { 117 /* The sequence below comes from Quark firmware writer guide */ 118 119 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, 120 1 << 1, (1 << 6) | (1 << 7)); 121 122 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG, 123 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10)); 124 125 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 126 127 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1); 128 129 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1, 130 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6); 131 132 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 133 134 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24); 135 } 136 137 static void quark_thermal_early_init(void) 138 { 139 /* The sequence below comes from Quark firmware writer guide */ 140 141 /* thermal sensor mode config */ 142 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 143 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5); 144 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 145 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | 146 (1 << 12), 1 << 9); 147 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14); 148 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17); 149 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18); 150 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f); 151 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17); 152 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 153 (1 << 8) | (1 << 9), 1 << 8); 154 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000); 155 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4, 156 0x7ff800, 0xc8 << 11); 157 158 /* thermal monitor catastrophic trip set point (105 celsius) */ 159 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155); 160 161 /* thermal monitor catastrophic trip clear point (0 celsius) */ 162 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16); 163 164 /* take thermal sensor out of reset */ 165 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0); 166 167 /* enable thermal monitor */ 168 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15); 169 170 /* lock all thermal configuration */ 171 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6)); 172 } 173 174 static void quark_enable_legacy_seg(void) 175 { 176 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2, 177 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 178 } 179 180 int arch_cpu_init(void) 181 { 182 int ret; 183 184 post_code(POST_CPU_INIT); 185 #ifdef CONFIG_SYS_X86_TSC_TIMER 186 timer_set_base(rdtsc()); 187 #endif 188 189 ret = x86_cpu_init_f(); 190 if (ret) 191 return ret; 192 193 /* 194 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 195 * which need be initialized with suggested values 196 */ 197 quark_setup_bars(); 198 199 /* 200 * Initialize PCIe controller 201 * 202 * Quark SoC holds the PCIe controller in reset following a power on. 203 * U-Boot needs to release the PCIe controller from reset. The PCIe 204 * controller (D23:F0/F1) will not be visible in PCI configuration 205 * space and any access to its PCI configuration registers will cause 206 * system hang while it is held in reset. 207 */ 208 quark_pcie_early_init(); 209 210 /* Initialize USB2 PHY */ 211 quark_usb_early_init(); 212 213 /* Initialize thermal sensor */ 214 quark_thermal_early_init(); 215 216 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 217 quark_enable_legacy_seg(); 218 219 unprotect_spi_flash(); 220 221 return 0; 222 } 223 224 int print_cpuinfo(void) 225 { 226 post_code(POST_CPU_INFO); 227 return default_print_cpuinfo(); 228 } 229 230 void reset_cpu(ulong addr) 231 { 232 /* cold reset */ 233 x86_full_reset(); 234 } 235 236 static void quark_pcie_init(void) 237 { 238 u32 val; 239 240 /* PCIe upstream non-posted & posted request size */ 241 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 242 CCFG_UPRS | CCFG_UNRS); 243 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 244 CCFG_UPRS | CCFG_UNRS); 245 246 /* PCIe packet fast transmit mode (IPF) */ 247 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 248 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 249 250 /* PCIe message bus idle counter (SBIC) */ 251 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 252 val |= MBC_SBIC; 253 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 254 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 255 val |= MBC_SBIC; 256 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 257 } 258 259 static void quark_usb_init(void) 260 { 261 u32 bar; 262 263 /* Change USB EHCI packet buffer OUT/IN threshold */ 264 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 265 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 266 267 /* Disable USB device interrupts */ 268 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 269 writel(0x7f, bar + USBD_INT_MASK); 270 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 271 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 272 } 273 274 int arch_early_init_r(void) 275 { 276 quark_pcie_init(); 277 278 quark_usb_init(); 279 280 return 0; 281 } 282 283 int cpu_mmc_init(bd_t *bis) 284 { 285 return pci_mmc_init("Quark SDHCI", mmc_supported, 286 ARRAY_SIZE(mmc_supported)); 287 } 288 289 void cpu_irq_init(void) 290 { 291 struct quark_rcba *rcba; 292 u32 base; 293 294 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 295 base &= ~MEM_BAR_EN; 296 rcba = (struct quark_rcba *)base; 297 298 /* 299 * Route Quark PCI device interrupt pin to PIRQ 300 * 301 * Route device#23's INTA/B/C/D to PIRQA/B/C/D 302 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H 303 */ 304 writew(PIRQC, &rcba->rmu_ir); 305 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), 306 &rcba->d23_ir); 307 writew(PIRQD, &rcba->core_ir); 308 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), 309 &rcba->d20d21_ir); 310 } 311 312 int arch_misc_init(void) 313 { 314 return pirq_init(); 315 } 316 317 void board_final_cleanup(void) 318 { 319 struct quark_rcba *rcba; 320 u32 base, val; 321 322 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 323 base &= ~MEM_BAR_EN; 324 rcba = (struct quark_rcba *)base; 325 326 /* Initialize 'Component ID' to zero */ 327 val = readl(&rcba->esd); 328 val &= ~0xff0000; 329 writel(val, &rcba->esd); 330 331 /* Lock HMBOUND for security */ 332 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK); 333 334 return; 335 } 336