1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <netdev.h> 10 #include <phy.h> 11 #include <asm/io.h> 12 #include <asm/irq.h> 13 #include <asm/pci.h> 14 #include <asm/post.h> 15 #include <asm/processor.h> 16 #include <asm/arch/device.h> 17 #include <asm/arch/msg_port.h> 18 #include <asm/arch/quark.h> 19 20 static struct pci_device_id mmc_supported[] = { 21 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 22 }; 23 24 /* 25 * TODO: 26 * 27 * This whole routine should be removed until we fully convert the ICH SPI 28 * driver to DM and make use of DT to pass the bios control register offset 29 */ 30 static void unprotect_spi_flash(void) 31 { 32 u32 bc; 33 34 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); 35 bc |= 0x1; /* unprotect the flash */ 36 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); 37 } 38 39 static void quark_setup_bars(void) 40 { 41 /* GPIO - D31:F0:R44h */ 42 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 43 CONFIG_GPIO_BASE | IO_BAR_EN); 44 45 /* ACPI PM1 Block - D31:F0:R48h */ 46 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 47 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 48 49 /* GPE0 - D31:F0:R4Ch */ 50 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 51 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 52 53 /* WDT - D31:F0:R84h */ 54 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 55 CONFIG_WDT_BASE | IO_BAR_EN); 56 57 /* RCBA - D31:F0:RF0h */ 58 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 59 CONFIG_RCBA_BASE | MEM_BAR_EN); 60 61 /* ACPI P Block - Msg Port 04:R70h */ 62 msg_port_write(MSG_PORT_RMU, PBLK_BA, 63 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 64 65 /* SPI DMA - Msg Port 04:R7Ah */ 66 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 67 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 68 69 /* PCIe ECAM */ 70 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 71 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 72 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 73 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 74 } 75 76 static void quark_pcie_early_init(void) 77 { 78 u32 pcie_cfg; 79 80 /* 81 * Step1: Assert PCIe signal PERST# 82 * 83 * The CPU interface to the PERST# signal is platform dependent. 84 * Call the board-specific codes to perform this task. 85 */ 86 board_assert_perst(); 87 88 /* Step2: PHY common lane reset */ 89 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 90 pcie_cfg |= PCIE_PHY_LANE_RST; 91 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 92 /* wait 1 ms for PHY common lane reset */ 93 mdelay(1); 94 95 /* Step3: PHY sideband interface reset and controller main reset */ 96 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 97 pcie_cfg |= (PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 98 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 99 /* wait 80ms for PLL to lock */ 100 mdelay(80); 101 102 /* Step4: Controller sideband interface reset */ 103 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 104 pcie_cfg |= PCIE_CTLR_SB_RST; 105 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 106 /* wait 20ms for controller sideband interface reset */ 107 mdelay(20); 108 109 /* Step5: De-assert PERST# */ 110 board_deassert_perst(); 111 112 /* Step6: Controller primary interface reset */ 113 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 114 pcie_cfg |= PCIE_CTLR_PRI_RST; 115 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 116 117 /* Mixer Load Lane 0 */ 118 pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0); 119 pcie_cfg &= ~((1 << 6) | (1 << 7)); 120 msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, pcie_cfg); 121 122 /* Mixer Load Lane 1 */ 123 pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1); 124 pcie_cfg &= ~((1 << 6) | (1 << 7)); 125 msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, pcie_cfg); 126 } 127 128 static void quark_enable_legacy_seg(void) 129 { 130 u32 hmisc2; 131 132 hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2); 133 hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 134 msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2); 135 } 136 137 int arch_cpu_init(void) 138 { 139 int ret; 140 141 post_code(POST_CPU_INIT); 142 #ifdef CONFIG_SYS_X86_TSC_TIMER 143 timer_set_base(rdtsc()); 144 #endif 145 146 ret = x86_cpu_init_f(); 147 if (ret) 148 return ret; 149 150 /* 151 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 152 * which need be initialized with suggested values 153 */ 154 quark_setup_bars(); 155 156 /* 157 * Initialize PCIe controller 158 * 159 * Quark SoC holds the PCIe controller in reset following a power on. 160 * U-Boot needs to release the PCIe controller from reset. The PCIe 161 * controller (D23:F0/F1) will not be visible in PCI configuration 162 * space and any access to its PCI configuration registers will cause 163 * system hang while it is held in reset. 164 */ 165 quark_pcie_early_init(); 166 167 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 168 quark_enable_legacy_seg(); 169 170 unprotect_spi_flash(); 171 172 return 0; 173 } 174 175 int print_cpuinfo(void) 176 { 177 post_code(POST_CPU_INFO); 178 return default_print_cpuinfo(); 179 } 180 181 void reset_cpu(ulong addr) 182 { 183 /* cold reset */ 184 x86_full_reset(); 185 } 186 187 int cpu_mmc_init(bd_t *bis) 188 { 189 return pci_mmc_init("Quark SDHCI", mmc_supported, 190 ARRAY_SIZE(mmc_supported)); 191 } 192 193 int cpu_eth_init(bd_t *bis) 194 { 195 u32 base; 196 int ret0, ret1; 197 198 qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base); 199 ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); 200 201 qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base); 202 ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); 203 204 if (ret0 < 0 && ret1 < 0) 205 return -1; 206 else 207 return 0; 208 } 209 210 void cpu_irq_init(void) 211 { 212 struct quark_rcba *rcba; 213 u32 base; 214 215 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 216 base &= ~MEM_BAR_EN; 217 rcba = (struct quark_rcba *)base; 218 219 /* 220 * Route Quark PCI device interrupt pin to PIRQ 221 * 222 * Route device#23's INTA/B/C/D to PIRQA/B/C/D 223 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H 224 */ 225 writew(PIRQC, &rcba->rmu_ir); 226 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), 227 &rcba->d23_ir); 228 writew(PIRQD, &rcba->core_ir); 229 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), 230 &rcba->d20d21_ir); 231 } 232 233 int arch_misc_init(void) 234 { 235 return pirq_init(); 236 } 237