1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <asm/io.h> 10 #include <asm/irq.h> 11 #include <asm/pci.h> 12 #include <asm/post.h> 13 #include <asm/processor.h> 14 #include <asm/arch/device.h> 15 #include <asm/arch/msg_port.h> 16 #include <asm/arch/quark.h> 17 18 static struct pci_device_id mmc_supported[] = { 19 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 20 }; 21 22 /* 23 * TODO: 24 * 25 * This whole routine should be removed until we fully convert the ICH SPI 26 * driver to DM and make use of DT to pass the bios control register offset 27 */ 28 static void unprotect_spi_flash(void) 29 { 30 u32 bc; 31 32 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); 33 bc |= 0x1; /* unprotect the flash */ 34 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); 35 } 36 37 static void quark_setup_bars(void) 38 { 39 /* GPIO - D31:F0:R44h */ 40 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 41 CONFIG_GPIO_BASE | IO_BAR_EN); 42 43 /* ACPI PM1 Block - D31:F0:R48h */ 44 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 45 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 46 47 /* GPE0 - D31:F0:R4Ch */ 48 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 49 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 50 51 /* WDT - D31:F0:R84h */ 52 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 53 CONFIG_WDT_BASE | IO_BAR_EN); 54 55 /* RCBA - D31:F0:RF0h */ 56 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 57 CONFIG_RCBA_BASE | MEM_BAR_EN); 58 59 /* ACPI P Block - Msg Port 04:R70h */ 60 msg_port_write(MSG_PORT_RMU, PBLK_BA, 61 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 62 63 /* SPI DMA - Msg Port 04:R7Ah */ 64 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 65 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 66 67 /* PCIe ECAM */ 68 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 69 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 70 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 71 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 72 } 73 74 static void quark_pcie_early_init(void) 75 { 76 u32 pcie_cfg; 77 78 /* 79 * Step1: Assert PCIe signal PERST# 80 * 81 * The CPU interface to the PERST# signal is platform dependent. 82 * Call the board-specific codes to perform this task. 83 */ 84 board_assert_perst(); 85 86 /* Step2: PHY common lane reset */ 87 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 88 pcie_cfg |= PCIE_PHY_LANE_RST; 89 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 90 /* wait 1 ms for PHY common lane reset */ 91 mdelay(1); 92 93 /* Step3: PHY sideband interface reset and controller main reset */ 94 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 95 pcie_cfg |= (PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 96 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 97 /* wait 80ms for PLL to lock */ 98 mdelay(80); 99 100 /* Step4: Controller sideband interface reset */ 101 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 102 pcie_cfg |= PCIE_CTLR_SB_RST; 103 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 104 /* wait 20ms for controller sideband interface reset */ 105 mdelay(20); 106 107 /* Step5: De-assert PERST# */ 108 board_deassert_perst(); 109 110 /* Step6: Controller primary interface reset */ 111 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG); 112 pcie_cfg |= PCIE_CTLR_PRI_RST; 113 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg); 114 115 /* Mixer Load Lane 0 */ 116 pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0); 117 pcie_cfg &= ~((1 << 6) | (1 << 7)); 118 msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, pcie_cfg); 119 120 /* Mixer Load Lane 1 */ 121 pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1); 122 pcie_cfg &= ~((1 << 6) | (1 << 7)); 123 msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, pcie_cfg); 124 } 125 126 static void quark_usb_early_init(void) 127 { 128 u32 usb; 129 130 /* The sequence below comes from Quark firmware writer guide */ 131 132 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT); 133 usb &= ~(1 << 1); 134 usb |= ((1 << 6) | (1 << 7)); 135 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, usb); 136 137 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_COMPBG); 138 usb &= ~((1 << 8) | (1 << 9)); 139 usb |= ((1 << 7) | (1 << 10)); 140 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_COMPBG, usb); 141 142 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2); 143 usb |= (1 << 29); 144 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb); 145 146 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1); 147 usb |= (1 << 1); 148 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb); 149 150 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1); 151 usb &= ~((1 << 3) | (1 << 4) | (1 << 5)); 152 usb |= (1 << 6); 153 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb); 154 155 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2); 156 usb &= ~(1 << 29); 157 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb); 158 159 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2); 160 usb |= (1 << 24); 161 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb); 162 } 163 164 static void quark_enable_legacy_seg(void) 165 { 166 u32 hmisc2; 167 168 hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2); 169 hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 170 msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2); 171 } 172 173 int arch_cpu_init(void) 174 { 175 int ret; 176 177 post_code(POST_CPU_INIT); 178 #ifdef CONFIG_SYS_X86_TSC_TIMER 179 timer_set_base(rdtsc()); 180 #endif 181 182 ret = x86_cpu_init_f(); 183 if (ret) 184 return ret; 185 186 /* 187 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 188 * which need be initialized with suggested values 189 */ 190 quark_setup_bars(); 191 192 /* 193 * Initialize PCIe controller 194 * 195 * Quark SoC holds the PCIe controller in reset following a power on. 196 * U-Boot needs to release the PCIe controller from reset. The PCIe 197 * controller (D23:F0/F1) will not be visible in PCI configuration 198 * space and any access to its PCI configuration registers will cause 199 * system hang while it is held in reset. 200 */ 201 quark_pcie_early_init(); 202 203 /* Initialize USB2 PHY */ 204 quark_usb_early_init(); 205 206 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 207 quark_enable_legacy_seg(); 208 209 unprotect_spi_flash(); 210 211 return 0; 212 } 213 214 int print_cpuinfo(void) 215 { 216 post_code(POST_CPU_INFO); 217 return default_print_cpuinfo(); 218 } 219 220 void reset_cpu(ulong addr) 221 { 222 /* cold reset */ 223 x86_full_reset(); 224 } 225 226 static void quark_pcie_init(void) 227 { 228 u32 val; 229 230 /* PCIe upstream non-posted & posted request size */ 231 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 232 CCFG_UPRS | CCFG_UNRS); 233 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 234 CCFG_UPRS | CCFG_UNRS); 235 236 /* PCIe packet fast transmit mode (IPF) */ 237 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 238 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 239 240 /* PCIe message bus idle counter (SBIC) */ 241 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 242 val |= MBC_SBIC; 243 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 244 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 245 val |= MBC_SBIC; 246 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 247 } 248 249 static void quark_usb_init(void) 250 { 251 u32 bar; 252 253 /* Change USB EHCI packet buffer OUT/IN threshold */ 254 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 255 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 256 257 /* Disable USB device interrupts */ 258 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 259 writel(0x7f, bar + USBD_INT_MASK); 260 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 261 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 262 } 263 264 int arch_early_init_r(void) 265 { 266 quark_pcie_init(); 267 268 quark_usb_init(); 269 270 return 0; 271 } 272 273 int cpu_mmc_init(bd_t *bis) 274 { 275 return pci_mmc_init("Quark SDHCI", mmc_supported, 276 ARRAY_SIZE(mmc_supported)); 277 } 278 279 void cpu_irq_init(void) 280 { 281 struct quark_rcba *rcba; 282 u32 base; 283 284 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 285 base &= ~MEM_BAR_EN; 286 rcba = (struct quark_rcba *)base; 287 288 /* 289 * Route Quark PCI device interrupt pin to PIRQ 290 * 291 * Route device#23's INTA/B/C/D to PIRQA/B/C/D 292 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H 293 */ 294 writew(PIRQC, &rcba->rmu_ir); 295 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), 296 &rcba->d23_ir); 297 writew(PIRQD, &rcba->core_ir); 298 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), 299 &rcba->d20d21_ir); 300 } 301 302 int arch_misc_init(void) 303 { 304 return pirq_init(); 305 } 306 307 void board_final_cleanup(void) 308 { 309 struct quark_rcba *rcba; 310 u32 base, val; 311 312 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 313 base &= ~MEM_BAR_EN; 314 rcba = (struct quark_rcba *)base; 315 316 /* Initialize 'Component ID' to zero */ 317 val = readl(&rcba->esd); 318 val &= ~0xff0000; 319 writel(val, &rcba->esd); 320 321 return; 322 } 323