1*8c30b571SSimon Glass /* 2*8c30b571SSimon Glass * Copyright (c) 2016 Google, Inc 3*8c30b571SSimon Glass * 4*8c30b571SSimon Glass * SPDX-License-Identifier: GPL-2.0 5*8c30b571SSimon Glass */ 6*8c30b571SSimon Glass 7*8c30b571SSimon Glass #include <common.h> 8*8c30b571SSimon Glass #include <dm.h> 9*8c30b571SSimon Glass #include <errno.h> 10*8c30b571SSimon Glass #include <fdtdec.h> 11*8c30b571SSimon Glass #include <pch.h> 12*8c30b571SSimon Glass #include <pci.h> 13*8c30b571SSimon Glass #include <asm/intel_regs.h> 14*8c30b571SSimon Glass #include <asm/io.h> 15*8c30b571SSimon Glass #include <asm/lpc_common.h> 16*8c30b571SSimon Glass 17*8c30b571SSimon Glass DECLARE_GLOBAL_DATA_PTR; 18*8c30b571SSimon Glass 19*8c30b571SSimon Glass /* Enable Prefetching and Caching */ 20*8c30b571SSimon Glass static void enable_spi_prefetch(struct udevice *pch) 21*8c30b571SSimon Glass { 22*8c30b571SSimon Glass u8 reg8; 23*8c30b571SSimon Glass 24*8c30b571SSimon Glass dm_pci_read_config8(pch, 0xdc, ®8); 25*8c30b571SSimon Glass reg8 &= ~(3 << 2); 26*8c30b571SSimon Glass reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 27*8c30b571SSimon Glass dm_pci_write_config8(pch, 0xdc, reg8); 28*8c30b571SSimon Glass } 29*8c30b571SSimon Glass 30*8c30b571SSimon Glass static void enable_port80_on_lpc(struct udevice *pch) 31*8c30b571SSimon Glass { 32*8c30b571SSimon Glass /* Enable port 80 POST on LPC */ 33*8c30b571SSimon Glass dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); 34*8c30b571SSimon Glass clrbits_le32(RCB_REG(GCS), 4); 35*8c30b571SSimon Glass } 36*8c30b571SSimon Glass 37*8c30b571SSimon Glass /** 38*8c30b571SSimon Glass * lpc_early_init() - set up LPC serial ports and other early things 39*8c30b571SSimon Glass * 40*8c30b571SSimon Glass * @dev: LPC device 41*8c30b571SSimon Glass * @return 0 if OK, -ve on error 42*8c30b571SSimon Glass */ 43*8c30b571SSimon Glass int lpc_common_early_init(struct udevice *dev) 44*8c30b571SSimon Glass { 45*8c30b571SSimon Glass struct udevice *pch = dev->parent; 46*8c30b571SSimon Glass struct reg_info { 47*8c30b571SSimon Glass u32 base; 48*8c30b571SSimon Glass u32 size; 49*8c30b571SSimon Glass } values[4], *ptr; 50*8c30b571SSimon Glass int count; 51*8c30b571SSimon Glass int i; 52*8c30b571SSimon Glass 53*8c30b571SSimon Glass count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, 54*8c30b571SSimon Glass "intel,gen-dec", (u32 *)values, 55*8c30b571SSimon Glass sizeof(values) / sizeof(u32)); 56*8c30b571SSimon Glass if (count < 0) 57*8c30b571SSimon Glass return -EINVAL; 58*8c30b571SSimon Glass 59*8c30b571SSimon Glass /* Set COM1/COM2 decode range */ 60*8c30b571SSimon Glass dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010); 61*8c30b571SSimon Glass 62*8c30b571SSimon Glass /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ 63*8c30b571SSimon Glass dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN | 64*8c30b571SSimon Glass GAMEL_LPC_EN | COMA_LPC_EN); 65*8c30b571SSimon Glass 66*8c30b571SSimon Glass /* Write all registers but use 0 if we run out of data */ 67*8c30b571SSimon Glass count = count * sizeof(u32) / sizeof(values[0]); 68*8c30b571SSimon Glass for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { 69*8c30b571SSimon Glass u32 reg = 0; 70*8c30b571SSimon Glass 71*8c30b571SSimon Glass if (i < count) 72*8c30b571SSimon Glass reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); 73*8c30b571SSimon Glass dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); 74*8c30b571SSimon Glass } 75*8c30b571SSimon Glass 76*8c30b571SSimon Glass enable_spi_prefetch(pch); 77*8c30b571SSimon Glass 78*8c30b571SSimon Glass /* This is already done in start.S, but let's do it in C */ 79*8c30b571SSimon Glass enable_port80_on_lpc(pch); 80*8c30b571SSimon Glass 81*8c30b571SSimon Glass return 0; 82*8c30b571SSimon Glass } 83*8c30b571SSimon Glass 84*8c30b571SSimon Glass int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect) 85*8c30b571SSimon Glass { 86*8c30b571SSimon Glass uint8_t bios_cntl; 87*8c30b571SSimon Glass 88*8c30b571SSimon Glass /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ 89*8c30b571SSimon Glass dm_pci_read_config8(dev, bios_ctrl, &bios_cntl); 90*8c30b571SSimon Glass if (protect) { 91*8c30b571SSimon Glass bios_cntl &= ~BIOS_CTRL_BIOSWE; 92*8c30b571SSimon Glass bios_cntl |= BIT(5); 93*8c30b571SSimon Glass } else { 94*8c30b571SSimon Glass bios_cntl |= BIOS_CTRL_BIOSWE; 95*8c30b571SSimon Glass bios_cntl &= ~BIT(5); 96*8c30b571SSimon Glass } 97*8c30b571SSimon Glass dm_pci_write_config8(dev, bios_ctrl, bios_cntl); 98*8c30b571SSimon Glass 99*8c30b571SSimon Glass return 0; 100*8c30b571SSimon Glass } 101