1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <errno.h> 22 #include <malloc.h> 23 #include <asm/control_regs.h> 24 #include <asm/cpu.h> 25 #include <asm/processor.h> 26 #include <asm/processor-flags.h> 27 #include <asm/interrupt.h> 28 #include <linux/compiler.h> 29 30 /* 31 * Constructor for a conventional segment GDT (or LDT) entry 32 * This is a macro so it can be used in initialisers 33 */ 34 #define GDT_ENTRY(flags, base, limit) \ 35 ((((base) & 0xff000000ULL) << (56-24)) | \ 36 (((flags) & 0x0000f0ffULL) << 40) | \ 37 (((limit) & 0x000f0000ULL) << (48-16)) | \ 38 (((base) & 0x00ffffffULL) << 16) | \ 39 (((limit) & 0x0000ffffULL))) 40 41 struct gdt_ptr { 42 u16 len; 43 u32 ptr; 44 } __packed; 45 46 static void load_ds(u32 segment) 47 { 48 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 49 } 50 51 static void load_es(u32 segment) 52 { 53 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 54 } 55 56 static void load_fs(u32 segment) 57 { 58 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 59 } 60 61 static void load_gs(u32 segment) 62 { 63 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 64 } 65 66 static void load_ss(u32 segment) 67 { 68 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 69 } 70 71 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 72 { 73 struct gdt_ptr gdt; 74 75 gdt.len = (num_entries * 8) - 1; 76 gdt.ptr = (u32)boot_gdt; 77 78 asm volatile("lgdtl %0\n" : : "m" (gdt)); 79 } 80 81 void setup_gdt(gd_t *id, u64 *gdt_addr) 82 { 83 /* CS: code, read/execute, 4 GB, base 0 */ 84 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 85 86 /* DS: data, read/write, 4 GB, base 0 */ 87 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 88 89 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 90 id->arch.gd_addr = id; 91 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 92 (ulong)&id->arch.gd_addr, 0xfffff); 93 94 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 95 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); 96 97 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 98 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); 99 100 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 101 load_ds(X86_GDT_ENTRY_32BIT_DS); 102 load_es(X86_GDT_ENTRY_32BIT_DS); 103 load_gs(X86_GDT_ENTRY_32BIT_DS); 104 load_ss(X86_GDT_ENTRY_32BIT_DS); 105 load_fs(X86_GDT_ENTRY_32BIT_FS); 106 } 107 108 int __weak x86_cleanup_before_linux(void) 109 { 110 #ifdef CONFIG_BOOTSTAGE_STASH 111 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, 112 CONFIG_BOOTSTAGE_STASH_SIZE); 113 #endif 114 115 return 0; 116 } 117 118 int x86_cpu_init_f(void) 119 { 120 const u32 em_rst = ~X86_CR0_EM; 121 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 122 123 /* initialize FPU, reset EM, set MP and NE */ 124 asm ("fninit\n" \ 125 "movl %%cr0, %%eax\n" \ 126 "andl %0, %%eax\n" \ 127 "orl %1, %%eax\n" \ 128 "movl %%eax, %%cr0\n" \ 129 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 130 131 return 0; 132 } 133 134 int x86_cpu_init_r(void) 135 { 136 /* Initialize core interrupt and exception functionality of CPU */ 137 cpu_init_interrupts(); 138 return 0; 139 } 140 int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); 141 142 void x86_enable_caches(void) 143 { 144 unsigned long cr0; 145 146 cr0 = read_cr0(); 147 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 148 write_cr0(cr0); 149 wbinvd(); 150 } 151 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 152 153 void x86_disable_caches(void) 154 { 155 unsigned long cr0; 156 157 cr0 = read_cr0(); 158 cr0 |= X86_CR0_NW | X86_CR0_CD; 159 wbinvd(); 160 write_cr0(cr0); 161 wbinvd(); 162 } 163 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 164 165 int x86_init_cache(void) 166 { 167 enable_caches(); 168 169 return 0; 170 } 171 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 172 173 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 174 { 175 printf("resetting ...\n"); 176 177 /* wait 50 ms */ 178 udelay(50000); 179 disable_interrupts(); 180 reset_cpu(0); 181 182 /*NOTREACHED*/ 183 return 0; 184 } 185 186 void flush_cache(unsigned long dummy1, unsigned long dummy2) 187 { 188 asm("wbinvd\n"); 189 } 190 191 void __attribute__ ((regparm(0))) generate_gpf(void); 192 193 /* segment 0x70 is an arbitrary segment which does not exist */ 194 asm(".globl generate_gpf\n" 195 ".hidden generate_gpf\n" 196 ".type generate_gpf, @function\n" 197 "generate_gpf:\n" 198 "ljmp $0x70, $0x47114711\n"); 199 200 __weak void reset_cpu(ulong addr) 201 { 202 printf("Resetting using x86 Triple Fault\n"); 203 set_vector(13, generate_gpf); /* general protection fault handler */ 204 set_vector(8, generate_gpf); /* double fault handler */ 205 generate_gpf(); /* start the show */ 206 } 207 208 int dcache_status(void) 209 { 210 return !(read_cr0() & 0x40000000); 211 } 212 213 /* Define these functions to allow ehch-hcd to function */ 214 void flush_dcache_range(unsigned long start, unsigned long stop) 215 { 216 } 217 218 void invalidate_dcache_range(unsigned long start, unsigned long stop) 219 { 220 } 221 222 void dcache_enable(void) 223 { 224 enable_caches(); 225 } 226 227 void dcache_disable(void) 228 { 229 disable_caches(); 230 } 231 232 void icache_enable(void) 233 { 234 } 235 236 void icache_disable(void) 237 { 238 } 239 240 int icache_status(void) 241 { 242 return 1; 243 } 244 245 void cpu_enable_paging_pae(ulong cr3) 246 { 247 __asm__ __volatile__( 248 /* Load the page table address */ 249 "movl %0, %%cr3\n" 250 /* Enable pae */ 251 "movl %%cr4, %%eax\n" 252 "orl $0x00000020, %%eax\n" 253 "movl %%eax, %%cr4\n" 254 /* Enable paging */ 255 "movl %%cr0, %%eax\n" 256 "orl $0x80000000, %%eax\n" 257 "movl %%eax, %%cr0\n" 258 : 259 : "r" (cr3) 260 : "eax"); 261 } 262 263 void cpu_disable_paging_pae(void) 264 { 265 /* Turn off paging */ 266 __asm__ __volatile__ ( 267 /* Disable paging */ 268 "movl %%cr0, %%eax\n" 269 "andl $0x7fffffff, %%eax\n" 270 "movl %%eax, %%cr0\n" 271 /* Disable pae */ 272 "movl %%cr4, %%eax\n" 273 "andl $0xffffffdf, %%eax\n" 274 "movl %%eax, %%cr4\n" 275 : 276 : 277 : "eax"); 278 } 279 280 static bool has_cpuid(void) 281 { 282 unsigned long flag; 283 284 asm volatile("pushf\n" \ 285 "pop %%eax\n" 286 "mov %%eax, %%ecx\n" /* ecx = flags */ 287 "xor %1, %%eax\n" 288 "push %%eax\n" 289 "popf\n" /* flags ^= $2 */ 290 "pushf\n" 291 "pop %%eax\n" /* eax = flags */ 292 "push %%ecx\n" 293 "popf\n" /* flags = ecx */ 294 "xor %%ecx, %%eax\n" 295 "mov %%eax, %0" 296 : "=r" (flag) 297 : "i" (1 << 21) 298 : "eax", "ecx", "memory"); 299 300 return flag != 0; 301 } 302 303 static bool can_detect_long_mode(void) 304 { 305 unsigned long flag; 306 307 asm volatile("mov $0x80000000, %%eax\n" 308 "cpuid\n" 309 "mov %%eax, %0" 310 : "=r" (flag) 311 : 312 : "eax", "ebx", "ecx", "edx", "memory"); 313 314 return flag > 0x80000000UL; 315 } 316 317 static bool has_long_mode(void) 318 { 319 unsigned long flag; 320 321 asm volatile("mov $0x80000001, %%eax\n" 322 "cpuid\n" 323 "mov %%edx, %0" 324 : "=r" (flag) 325 : 326 : "eax", "ebx", "ecx", "edx", "memory"); 327 328 return flag & (1 << 29) ? true : false; 329 } 330 331 int cpu_has_64bit(void) 332 { 333 return has_cpuid() && can_detect_long_mode() && 334 has_long_mode(); 335 } 336 337 int print_cpuinfo(void) 338 { 339 printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86"); 340 341 return 0; 342 } 343 344 #define PAGETABLE_SIZE (6 * 4096) 345 346 /** 347 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 348 * 349 * @pgtable: Pointer to a 24iKB block of memory 350 */ 351 static void build_pagetable(uint32_t *pgtable) 352 { 353 uint i; 354 355 memset(pgtable, '\0', PAGETABLE_SIZE); 356 357 /* Level 4 needs a single entry */ 358 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 359 360 /* Level 3 has one 64-bit entry for each GiB of memory */ 361 for (i = 0; i < 4; i++) { 362 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 363 0x1000 * i + 7; 364 } 365 366 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 367 for (i = 0; i < 2048; i++) 368 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 369 } 370 371 int cpu_jump_to_64bit(ulong setup_base, ulong target) 372 { 373 uint32_t *pgtable; 374 375 pgtable = memalign(4096, PAGETABLE_SIZE); 376 if (!pgtable) 377 return -ENOMEM; 378 379 build_pagetable(pgtable); 380 cpu_call64((ulong)pgtable, setup_base, target); 381 free(pgtable); 382 383 return -EFAULT; 384 } 385