1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <errno.h> 25 #include <malloc.h> 26 #include <asm/control_regs.h> 27 #include <asm/cpu.h> 28 #include <asm/processor.h> 29 #include <asm/processor-flags.h> 30 #include <asm/interrupt.h> 31 #include <linux/compiler.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* 36 * Constructor for a conventional segment GDT (or LDT) entry 37 * This is a macro so it can be used in initialisers 38 */ 39 #define GDT_ENTRY(flags, base, limit) \ 40 ((((base) & 0xff000000ULL) << (56-24)) | \ 41 (((flags) & 0x0000f0ffULL) << 40) | \ 42 (((limit) & 0x000f0000ULL) << (48-16)) | \ 43 (((base) & 0x00ffffffULL) << 16) | \ 44 (((limit) & 0x0000ffffULL))) 45 46 struct gdt_ptr { 47 u16 len; 48 u32 ptr; 49 } __packed; 50 51 struct cpu_device_id { 52 unsigned vendor; 53 unsigned device; 54 }; 55 56 struct cpuinfo_x86 { 57 uint8_t x86; /* CPU family */ 58 uint8_t x86_vendor; /* CPU vendor */ 59 uint8_t x86_model; 60 uint8_t x86_mask; 61 }; 62 63 /* 64 * List of cpu vendor strings along with their normalized 65 * id values. 66 */ 67 static struct { 68 int vendor; 69 const char *name; 70 } x86_vendors[] = { 71 { X86_VENDOR_INTEL, "GenuineIntel", }, 72 { X86_VENDOR_CYRIX, "CyrixInstead", }, 73 { X86_VENDOR_AMD, "AuthenticAMD", }, 74 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 75 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 76 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 77 { X86_VENDOR_RISE, "RiseRiseRise", }, 78 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 79 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 80 { X86_VENDOR_NSC, "Geode by NSC", }, 81 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 82 }; 83 84 static const char *const x86_vendor_name[] = { 85 [X86_VENDOR_INTEL] = "Intel", 86 [X86_VENDOR_CYRIX] = "Cyrix", 87 [X86_VENDOR_AMD] = "AMD", 88 [X86_VENDOR_UMC] = "UMC", 89 [X86_VENDOR_NEXGEN] = "NexGen", 90 [X86_VENDOR_CENTAUR] = "Centaur", 91 [X86_VENDOR_RISE] = "Rise", 92 [X86_VENDOR_TRANSMETA] = "Transmeta", 93 [X86_VENDOR_NSC] = "NSC", 94 [X86_VENDOR_SIS] = "SiS", 95 }; 96 97 static void load_ds(u32 segment) 98 { 99 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 100 } 101 102 static void load_es(u32 segment) 103 { 104 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 105 } 106 107 static void load_fs(u32 segment) 108 { 109 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 110 } 111 112 static void load_gs(u32 segment) 113 { 114 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 115 } 116 117 static void load_ss(u32 segment) 118 { 119 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 120 } 121 122 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 123 { 124 struct gdt_ptr gdt; 125 126 gdt.len = (num_entries * 8) - 1; 127 gdt.ptr = (u32)boot_gdt; 128 129 asm volatile("lgdtl %0\n" : : "m" (gdt)); 130 } 131 132 void setup_gdt(gd_t *id, u64 *gdt_addr) 133 { 134 /* CS: code, read/execute, 4 GB, base 0 */ 135 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 136 137 /* DS: data, read/write, 4 GB, base 0 */ 138 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 139 140 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 141 id->arch.gd_addr = id; 142 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 143 (ulong)&id->arch.gd_addr, 0xfffff); 144 145 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 146 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); 147 148 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 149 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); 150 151 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 152 load_ds(X86_GDT_ENTRY_32BIT_DS); 153 load_es(X86_GDT_ENTRY_32BIT_DS); 154 load_gs(X86_GDT_ENTRY_32BIT_DS); 155 load_ss(X86_GDT_ENTRY_32BIT_DS); 156 load_fs(X86_GDT_ENTRY_32BIT_FS); 157 } 158 159 int __weak x86_cleanup_before_linux(void) 160 { 161 #ifdef CONFIG_BOOTSTAGE_STASH 162 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, 163 CONFIG_BOOTSTAGE_STASH_SIZE); 164 #endif 165 166 return 0; 167 } 168 169 /* 170 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 171 * by the fact that they preserve the flags across the division of 5/2. 172 * PII and PPro exhibit this behavior too, but they have cpuid available. 173 */ 174 175 /* 176 * Perform the Cyrix 5/2 test. A Cyrix won't change 177 * the flags, while other 486 chips will. 178 */ 179 static inline int test_cyrix_52div(void) 180 { 181 unsigned int test; 182 183 __asm__ __volatile__( 184 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 185 "div %b2\n\t" /* divide 5 by 2 */ 186 "lahf" /* store flags into %ah */ 187 : "=a" (test) 188 : "0" (5), "q" (2) 189 : "cc"); 190 191 /* AH is 0x02 on Cyrix after the divide.. */ 192 return (unsigned char) (test >> 8) == 0x02; 193 } 194 195 /* 196 * Detect a NexGen CPU running without BIOS hypercode new enough 197 * to have CPUID. (Thanks to Herbert Oppmann) 198 */ 199 200 static int deep_magic_nexgen_probe(void) 201 { 202 int ret; 203 204 __asm__ __volatile__ ( 205 " movw $0x5555, %%ax\n" 206 " xorw %%dx,%%dx\n" 207 " movw $2, %%cx\n" 208 " divw %%cx\n" 209 " movl $0, %%eax\n" 210 " jnz 1f\n" 211 " movl $1, %%eax\n" 212 "1:\n" 213 : "=a" (ret) : : "cx", "dx"); 214 return ret; 215 } 216 217 static bool has_cpuid(void) 218 { 219 return flag_is_changeable_p(X86_EFLAGS_ID); 220 } 221 222 static int build_vendor_name(char *vendor_name) 223 { 224 struct cpuid_result result; 225 result = cpuid(0x00000000); 226 unsigned int *name_as_ints = (unsigned int *)vendor_name; 227 228 name_as_ints[0] = result.ebx; 229 name_as_ints[1] = result.edx; 230 name_as_ints[2] = result.ecx; 231 232 return result.eax; 233 } 234 235 static void identify_cpu(struct cpu_device_id *cpu) 236 { 237 char vendor_name[16]; 238 int i; 239 240 vendor_name[0] = '\0'; /* Unset */ 241 cpu->device = 0; /* fix gcc 4.4.4 warning */ 242 243 /* Find the id and vendor_name */ 244 if (!has_cpuid()) { 245 /* Its a 486 if we can modify the AC flag */ 246 if (flag_is_changeable_p(X86_EFLAGS_AC)) 247 cpu->device = 0x00000400; /* 486 */ 248 else 249 cpu->device = 0x00000300; /* 386 */ 250 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 251 memcpy(vendor_name, "CyrixInstead", 13); 252 /* If we ever care we can enable cpuid here */ 253 } 254 /* Detect NexGen with old hypercode */ 255 else if (deep_magic_nexgen_probe()) 256 memcpy(vendor_name, "NexGenDriven", 13); 257 } 258 if (has_cpuid()) { 259 int cpuid_level; 260 261 cpuid_level = build_vendor_name(vendor_name); 262 vendor_name[12] = '\0'; 263 264 /* Intel-defined flags: level 0x00000001 */ 265 if (cpuid_level >= 0x00000001) { 266 cpu->device = cpuid_eax(0x00000001); 267 } else { 268 /* Have CPUID level 0 only unheard of */ 269 cpu->device = 0x00000400; 270 } 271 } 272 cpu->vendor = X86_VENDOR_UNKNOWN; 273 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 274 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 275 cpu->vendor = x86_vendors[i].vendor; 276 break; 277 } 278 } 279 } 280 281 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 282 { 283 c->x86 = (tfms >> 8) & 0xf; 284 c->x86_model = (tfms >> 4) & 0xf; 285 c->x86_mask = tfms & 0xf; 286 if (c->x86 == 0xf) 287 c->x86 += (tfms >> 20) & 0xff; 288 if (c->x86 >= 0x6) 289 c->x86_model += ((tfms >> 16) & 0xF) << 4; 290 } 291 292 int x86_cpu_init_f(void) 293 { 294 const u32 em_rst = ~X86_CR0_EM; 295 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 296 297 /* initialize FPU, reset EM, set MP and NE */ 298 asm ("fninit\n" \ 299 "movl %%cr0, %%eax\n" \ 300 "andl %0, %%eax\n" \ 301 "orl %1, %%eax\n" \ 302 "movl %%eax, %%cr0\n" \ 303 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 304 305 /* identify CPU via cpuid and store the decoded info into gd->arch */ 306 if (has_cpuid()) { 307 struct cpu_device_id cpu; 308 struct cpuinfo_x86 c; 309 310 identify_cpu(&cpu); 311 get_fms(&c, cpu.device); 312 gd->arch.x86 = c.x86; 313 gd->arch.x86_vendor = cpu.vendor; 314 gd->arch.x86_model = c.x86_model; 315 gd->arch.x86_mask = c.x86_mask; 316 gd->arch.x86_device = cpu.device; 317 } 318 319 return 0; 320 } 321 322 int x86_cpu_init_r(void) 323 { 324 /* Initialize core interrupt and exception functionality of CPU */ 325 cpu_init_interrupts(); 326 return 0; 327 } 328 int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); 329 330 void x86_enable_caches(void) 331 { 332 unsigned long cr0; 333 334 cr0 = read_cr0(); 335 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 336 write_cr0(cr0); 337 wbinvd(); 338 } 339 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 340 341 void x86_disable_caches(void) 342 { 343 unsigned long cr0; 344 345 cr0 = read_cr0(); 346 cr0 |= X86_CR0_NW | X86_CR0_CD; 347 wbinvd(); 348 write_cr0(cr0); 349 wbinvd(); 350 } 351 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 352 353 int x86_init_cache(void) 354 { 355 enable_caches(); 356 357 return 0; 358 } 359 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 360 361 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 362 { 363 printf("resetting ...\n"); 364 365 /* wait 50 ms */ 366 udelay(50000); 367 disable_interrupts(); 368 reset_cpu(0); 369 370 /*NOTREACHED*/ 371 return 0; 372 } 373 374 void flush_cache(unsigned long dummy1, unsigned long dummy2) 375 { 376 asm("wbinvd\n"); 377 } 378 379 void __attribute__ ((regparm(0))) generate_gpf(void); 380 381 /* segment 0x70 is an arbitrary segment which does not exist */ 382 asm(".globl generate_gpf\n" 383 ".hidden generate_gpf\n" 384 ".type generate_gpf, @function\n" 385 "generate_gpf:\n" 386 "ljmp $0x70, $0x47114711\n"); 387 388 __weak void reset_cpu(ulong addr) 389 { 390 printf("Resetting using x86 Triple Fault\n"); 391 set_vector(13, generate_gpf); /* general protection fault handler */ 392 set_vector(8, generate_gpf); /* double fault handler */ 393 generate_gpf(); /* start the show */ 394 } 395 396 int dcache_status(void) 397 { 398 return !(read_cr0() & 0x40000000); 399 } 400 401 /* Define these functions to allow ehch-hcd to function */ 402 void flush_dcache_range(unsigned long start, unsigned long stop) 403 { 404 } 405 406 void invalidate_dcache_range(unsigned long start, unsigned long stop) 407 { 408 } 409 410 void dcache_enable(void) 411 { 412 enable_caches(); 413 } 414 415 void dcache_disable(void) 416 { 417 disable_caches(); 418 } 419 420 void icache_enable(void) 421 { 422 } 423 424 void icache_disable(void) 425 { 426 } 427 428 int icache_status(void) 429 { 430 return 1; 431 } 432 433 void cpu_enable_paging_pae(ulong cr3) 434 { 435 __asm__ __volatile__( 436 /* Load the page table address */ 437 "movl %0, %%cr3\n" 438 /* Enable pae */ 439 "movl %%cr4, %%eax\n" 440 "orl $0x00000020, %%eax\n" 441 "movl %%eax, %%cr4\n" 442 /* Enable paging */ 443 "movl %%cr0, %%eax\n" 444 "orl $0x80000000, %%eax\n" 445 "movl %%eax, %%cr0\n" 446 : 447 : "r" (cr3) 448 : "eax"); 449 } 450 451 void cpu_disable_paging_pae(void) 452 { 453 /* Turn off paging */ 454 __asm__ __volatile__ ( 455 /* Disable paging */ 456 "movl %%cr0, %%eax\n" 457 "andl $0x7fffffff, %%eax\n" 458 "movl %%eax, %%cr0\n" 459 /* Disable pae */ 460 "movl %%cr4, %%eax\n" 461 "andl $0xffffffdf, %%eax\n" 462 "movl %%eax, %%cr4\n" 463 : 464 : 465 : "eax"); 466 } 467 468 static bool can_detect_long_mode(void) 469 { 470 return cpuid_eax(0x80000000) > 0x80000000UL; 471 } 472 473 static bool has_long_mode(void) 474 { 475 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 476 } 477 478 int cpu_has_64bit(void) 479 { 480 return has_cpuid() && can_detect_long_mode() && 481 has_long_mode(); 482 } 483 484 const char *cpu_vendor_name(int vendor) 485 { 486 const char *name; 487 name = "<invalid cpu vendor>"; 488 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 489 (x86_vendor_name[vendor] != 0)) 490 name = x86_vendor_name[vendor]; 491 492 return name; 493 } 494 495 void fill_processor_name(char *processor_name) 496 { 497 struct cpuid_result regs; 498 char temp_processor_name[49]; 499 char *processor_name_start; 500 unsigned int *name_as_ints = (unsigned int *)temp_processor_name; 501 int i; 502 503 for (i = 0; i < 3; i++) { 504 regs = cpuid(0x80000002 + i); 505 name_as_ints[i * 4 + 0] = regs.eax; 506 name_as_ints[i * 4 + 1] = regs.ebx; 507 name_as_ints[i * 4 + 2] = regs.ecx; 508 name_as_ints[i * 4 + 3] = regs.edx; 509 } 510 511 temp_processor_name[48] = 0; 512 513 /* Skip leading spaces. */ 514 processor_name_start = temp_processor_name; 515 while (*processor_name_start == ' ') 516 processor_name_start++; 517 518 memset(processor_name, 0, 49); 519 strcpy(processor_name, processor_name_start); 520 } 521 522 int print_cpuinfo(void) 523 { 524 printf("CPU: %s, vendor %s, device %xh\n", 525 cpu_has_64bit() ? "x86_64" : "x86", 526 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 527 528 return 0; 529 } 530 531 #define PAGETABLE_SIZE (6 * 4096) 532 533 /** 534 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 535 * 536 * @pgtable: Pointer to a 24iKB block of memory 537 */ 538 static void build_pagetable(uint32_t *pgtable) 539 { 540 uint i; 541 542 memset(pgtable, '\0', PAGETABLE_SIZE); 543 544 /* Level 4 needs a single entry */ 545 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 546 547 /* Level 3 has one 64-bit entry for each GiB of memory */ 548 for (i = 0; i < 4; i++) { 549 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 550 0x1000 * i + 7; 551 } 552 553 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 554 for (i = 0; i < 2048; i++) 555 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 556 } 557 558 int cpu_jump_to_64bit(ulong setup_base, ulong target) 559 { 560 uint32_t *pgtable; 561 562 pgtable = memalign(4096, PAGETABLE_SIZE); 563 if (!pgtable) 564 return -ENOMEM; 565 566 build_pagetable(pgtable); 567 cpu_call64((ulong)pgtable, setup_base, target); 568 free(pgtable); 569 570 return -EFAULT; 571 } 572