1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <asm/control_regs.h> 28 #include <asm/cpu.h> 29 #include <asm/lapic.h> 30 #include <asm/mp.h> 31 #include <asm/msr.h> 32 #include <asm/mtrr.h> 33 #include <asm/post.h> 34 #include <asm/processor.h> 35 #include <asm/processor-flags.h> 36 #include <asm/interrupt.h> 37 #include <asm/tables.h> 38 #include <linux/compiler.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* 43 * Constructor for a conventional segment GDT (or LDT) entry 44 * This is a macro so it can be used in initialisers 45 */ 46 #define GDT_ENTRY(flags, base, limit) \ 47 ((((base) & 0xff000000ULL) << (56-24)) | \ 48 (((flags) & 0x0000f0ffULL) << 40) | \ 49 (((limit) & 0x000f0000ULL) << (48-16)) | \ 50 (((base) & 0x00ffffffULL) << 16) | \ 51 (((limit) & 0x0000ffffULL))) 52 53 struct gdt_ptr { 54 u16 len; 55 u32 ptr; 56 } __packed; 57 58 struct cpu_device_id { 59 unsigned vendor; 60 unsigned device; 61 }; 62 63 struct cpuinfo_x86 { 64 uint8_t x86; /* CPU family */ 65 uint8_t x86_vendor; /* CPU vendor */ 66 uint8_t x86_model; 67 uint8_t x86_mask; 68 }; 69 70 /* 71 * List of cpu vendor strings along with their normalized 72 * id values. 73 */ 74 static const struct { 75 int vendor; 76 const char *name; 77 } x86_vendors[] = { 78 { X86_VENDOR_INTEL, "GenuineIntel", }, 79 { X86_VENDOR_CYRIX, "CyrixInstead", }, 80 { X86_VENDOR_AMD, "AuthenticAMD", }, 81 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 82 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 83 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 84 { X86_VENDOR_RISE, "RiseRiseRise", }, 85 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 86 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 87 { X86_VENDOR_NSC, "Geode by NSC", }, 88 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 89 }; 90 91 static const char *const x86_vendor_name[] = { 92 [X86_VENDOR_INTEL] = "Intel", 93 [X86_VENDOR_CYRIX] = "Cyrix", 94 [X86_VENDOR_AMD] = "AMD", 95 [X86_VENDOR_UMC] = "UMC", 96 [X86_VENDOR_NEXGEN] = "NexGen", 97 [X86_VENDOR_CENTAUR] = "Centaur", 98 [X86_VENDOR_RISE] = "Rise", 99 [X86_VENDOR_TRANSMETA] = "Transmeta", 100 [X86_VENDOR_NSC] = "NSC", 101 [X86_VENDOR_SIS] = "SiS", 102 }; 103 104 static void load_ds(u32 segment) 105 { 106 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 107 } 108 109 static void load_es(u32 segment) 110 { 111 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 112 } 113 114 static void load_fs(u32 segment) 115 { 116 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 117 } 118 119 static void load_gs(u32 segment) 120 { 121 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 122 } 123 124 static void load_ss(u32 segment) 125 { 126 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 127 } 128 129 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 130 { 131 struct gdt_ptr gdt; 132 133 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 134 gdt.ptr = (u32)boot_gdt; 135 136 asm volatile("lgdtl %0\n" : : "m" (gdt)); 137 } 138 139 void arch_setup_gd(gd_t *new_gd) 140 { 141 u64 *gdt_addr; 142 143 gdt_addr = new_gd->arch.gdt; 144 145 /* 146 * CS: code, read/execute, 4 GB, base 0 147 * 148 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS 149 */ 150 gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); 151 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 152 153 /* DS: data, read/write, 4 GB, base 0 */ 154 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 155 156 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 157 new_gd->arch.gd_addr = new_gd; 158 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 159 (ulong)&new_gd->arch.gd_addr, 0xfffff); 160 161 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 162 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 163 164 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 165 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 166 167 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 168 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 169 170 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 171 load_ds(X86_GDT_ENTRY_32BIT_DS); 172 load_es(X86_GDT_ENTRY_32BIT_DS); 173 load_gs(X86_GDT_ENTRY_32BIT_DS); 174 load_ss(X86_GDT_ENTRY_32BIT_DS); 175 load_fs(X86_GDT_ENTRY_32BIT_FS); 176 } 177 178 #ifdef CONFIG_HAVE_FSP 179 /* 180 * Setup FSP execution environment GDT 181 * 182 * Per Intel FSP external architecture specification, before calling any FSP 183 * APIs, we need make sure the system is in flat 32-bit mode and both the code 184 * and data selectors should have full 4GB access range. Here we reuse the one 185 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 186 */ 187 void setup_fsp_gdt(void) 188 { 189 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 190 load_ds(X86_GDT_ENTRY_32BIT_DS); 191 load_ss(X86_GDT_ENTRY_32BIT_DS); 192 load_es(X86_GDT_ENTRY_32BIT_DS); 193 load_fs(X86_GDT_ENTRY_32BIT_DS); 194 load_gs(X86_GDT_ENTRY_32BIT_DS); 195 } 196 #endif 197 198 int __weak x86_cleanup_before_linux(void) 199 { 200 #ifdef CONFIG_BOOTSTAGE_STASH 201 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 202 CONFIG_BOOTSTAGE_STASH_SIZE); 203 #endif 204 205 return 0; 206 } 207 208 /* 209 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 210 * by the fact that they preserve the flags across the division of 5/2. 211 * PII and PPro exhibit this behavior too, but they have cpuid available. 212 */ 213 214 /* 215 * Perform the Cyrix 5/2 test. A Cyrix won't change 216 * the flags, while other 486 chips will. 217 */ 218 static inline int test_cyrix_52div(void) 219 { 220 unsigned int test; 221 222 __asm__ __volatile__( 223 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 224 "div %b2\n\t" /* divide 5 by 2 */ 225 "lahf" /* store flags into %ah */ 226 : "=a" (test) 227 : "0" (5), "q" (2) 228 : "cc"); 229 230 /* AH is 0x02 on Cyrix after the divide.. */ 231 return (unsigned char) (test >> 8) == 0x02; 232 } 233 234 /* 235 * Detect a NexGen CPU running without BIOS hypercode new enough 236 * to have CPUID. (Thanks to Herbert Oppmann) 237 */ 238 239 static int deep_magic_nexgen_probe(void) 240 { 241 int ret; 242 243 __asm__ __volatile__ ( 244 " movw $0x5555, %%ax\n" 245 " xorw %%dx,%%dx\n" 246 " movw $2, %%cx\n" 247 " divw %%cx\n" 248 " movl $0, %%eax\n" 249 " jnz 1f\n" 250 " movl $1, %%eax\n" 251 "1:\n" 252 : "=a" (ret) : : "cx", "dx"); 253 return ret; 254 } 255 256 static bool has_cpuid(void) 257 { 258 return flag_is_changeable_p(X86_EFLAGS_ID); 259 } 260 261 static bool has_mtrr(void) 262 { 263 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 264 } 265 266 static int build_vendor_name(char *vendor_name) 267 { 268 struct cpuid_result result; 269 result = cpuid(0x00000000); 270 unsigned int *name_as_ints = (unsigned int *)vendor_name; 271 272 name_as_ints[0] = result.ebx; 273 name_as_ints[1] = result.edx; 274 name_as_ints[2] = result.ecx; 275 276 return result.eax; 277 } 278 279 static void identify_cpu(struct cpu_device_id *cpu) 280 { 281 char vendor_name[16]; 282 int i; 283 284 vendor_name[0] = '\0'; /* Unset */ 285 cpu->device = 0; /* fix gcc 4.4.4 warning */ 286 287 /* Find the id and vendor_name */ 288 if (!has_cpuid()) { 289 /* Its a 486 if we can modify the AC flag */ 290 if (flag_is_changeable_p(X86_EFLAGS_AC)) 291 cpu->device = 0x00000400; /* 486 */ 292 else 293 cpu->device = 0x00000300; /* 386 */ 294 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 295 memcpy(vendor_name, "CyrixInstead", 13); 296 /* If we ever care we can enable cpuid here */ 297 } 298 /* Detect NexGen with old hypercode */ 299 else if (deep_magic_nexgen_probe()) 300 memcpy(vendor_name, "NexGenDriven", 13); 301 } 302 if (has_cpuid()) { 303 int cpuid_level; 304 305 cpuid_level = build_vendor_name(vendor_name); 306 vendor_name[12] = '\0'; 307 308 /* Intel-defined flags: level 0x00000001 */ 309 if (cpuid_level >= 0x00000001) { 310 cpu->device = cpuid_eax(0x00000001); 311 } else { 312 /* Have CPUID level 0 only unheard of */ 313 cpu->device = 0x00000400; 314 } 315 } 316 cpu->vendor = X86_VENDOR_UNKNOWN; 317 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 318 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 319 cpu->vendor = x86_vendors[i].vendor; 320 break; 321 } 322 } 323 } 324 325 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 326 { 327 c->x86 = (tfms >> 8) & 0xf; 328 c->x86_model = (tfms >> 4) & 0xf; 329 c->x86_mask = tfms & 0xf; 330 if (c->x86 == 0xf) 331 c->x86 += (tfms >> 20) & 0xff; 332 if (c->x86 >= 0x6) 333 c->x86_model += ((tfms >> 16) & 0xF) << 4; 334 } 335 336 u32 cpu_get_family_model(void) 337 { 338 return gd->arch.x86_device & 0x0fff0ff0; 339 } 340 341 u32 cpu_get_stepping(void) 342 { 343 return gd->arch.x86_mask; 344 } 345 346 int x86_cpu_init_f(void) 347 { 348 const u32 em_rst = ~X86_CR0_EM; 349 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 350 351 if (ll_boot_init()) { 352 /* initialize FPU, reset EM, set MP and NE */ 353 asm ("fninit\n" \ 354 "movl %%cr0, %%eax\n" \ 355 "andl %0, %%eax\n" \ 356 "orl %1, %%eax\n" \ 357 "movl %%eax, %%cr0\n" \ 358 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 359 } 360 361 /* identify CPU via cpuid and store the decoded info into gd->arch */ 362 if (has_cpuid()) { 363 struct cpu_device_id cpu; 364 struct cpuinfo_x86 c; 365 366 identify_cpu(&cpu); 367 get_fms(&c, cpu.device); 368 gd->arch.x86 = c.x86; 369 gd->arch.x86_vendor = cpu.vendor; 370 gd->arch.x86_model = c.x86_model; 371 gd->arch.x86_mask = c.x86_mask; 372 gd->arch.x86_device = cpu.device; 373 374 gd->arch.has_mtrr = has_mtrr(); 375 } 376 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ 377 gd->pci_ram_top = 0x80000000U; 378 379 /* Configure fixed range MTRRs for some legacy regions */ 380 if (gd->arch.has_mtrr) { 381 u64 mtrr_cap; 382 383 mtrr_cap = native_read_msr(MTRR_CAP_MSR); 384 if (mtrr_cap & MTRR_CAP_FIX) { 385 /* Mark the VGA RAM area as uncacheable */ 386 native_write_msr(MTRR_FIX_16K_A0000_MSR, 387 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), 388 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 389 390 /* 391 * Mark the PCI ROM area as cacheable to improve ROM 392 * execution performance. 393 */ 394 native_write_msr(MTRR_FIX_4K_C0000_MSR, 395 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 396 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 397 native_write_msr(MTRR_FIX_4K_C8000_MSR, 398 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 399 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 400 native_write_msr(MTRR_FIX_4K_D0000_MSR, 401 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 402 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 403 native_write_msr(MTRR_FIX_4K_D8000_MSR, 404 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 405 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 406 407 /* Enable the fixed range MTRRs */ 408 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); 409 } 410 } 411 412 #ifdef CONFIG_I8254_TIMER 413 /* Set up the i8254 timer if required */ 414 i8254_init(); 415 #endif 416 417 return 0; 418 } 419 420 void x86_enable_caches(void) 421 { 422 unsigned long cr0; 423 424 cr0 = read_cr0(); 425 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 426 write_cr0(cr0); 427 wbinvd(); 428 } 429 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 430 431 void x86_disable_caches(void) 432 { 433 unsigned long cr0; 434 435 cr0 = read_cr0(); 436 cr0 |= X86_CR0_NW | X86_CR0_CD; 437 wbinvd(); 438 write_cr0(cr0); 439 wbinvd(); 440 } 441 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 442 443 int x86_init_cache(void) 444 { 445 enable_caches(); 446 447 return 0; 448 } 449 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 450 451 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 452 { 453 printf("resetting ...\n"); 454 455 /* wait 50 ms */ 456 udelay(50000); 457 disable_interrupts(); 458 reset_cpu(0); 459 460 /*NOTREACHED*/ 461 return 0; 462 } 463 464 void flush_cache(unsigned long dummy1, unsigned long dummy2) 465 { 466 asm("wbinvd\n"); 467 } 468 469 __weak void reset_cpu(ulong addr) 470 { 471 /* Do a hard reset through the chipset's reset control register */ 472 outb(SYS_RST | RST_CPU, PORT_RESET); 473 for (;;) 474 cpu_hlt(); 475 } 476 477 void x86_full_reset(void) 478 { 479 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 480 } 481 482 int dcache_status(void) 483 { 484 return !(read_cr0() & X86_CR0_CD); 485 } 486 487 /* Define these functions to allow ehch-hcd to function */ 488 void flush_dcache_range(unsigned long start, unsigned long stop) 489 { 490 } 491 492 void invalidate_dcache_range(unsigned long start, unsigned long stop) 493 { 494 } 495 496 void dcache_enable(void) 497 { 498 enable_caches(); 499 } 500 501 void dcache_disable(void) 502 { 503 disable_caches(); 504 } 505 506 void icache_enable(void) 507 { 508 } 509 510 void icache_disable(void) 511 { 512 } 513 514 int icache_status(void) 515 { 516 return 1; 517 } 518 519 void cpu_enable_paging_pae(ulong cr3) 520 { 521 __asm__ __volatile__( 522 /* Load the page table address */ 523 "movl %0, %%cr3\n" 524 /* Enable pae */ 525 "movl %%cr4, %%eax\n" 526 "orl $0x00000020, %%eax\n" 527 "movl %%eax, %%cr4\n" 528 /* Enable paging */ 529 "movl %%cr0, %%eax\n" 530 "orl $0x80000000, %%eax\n" 531 "movl %%eax, %%cr0\n" 532 : 533 : "r" (cr3) 534 : "eax"); 535 } 536 537 void cpu_disable_paging_pae(void) 538 { 539 /* Turn off paging */ 540 __asm__ __volatile__ ( 541 /* Disable paging */ 542 "movl %%cr0, %%eax\n" 543 "andl $0x7fffffff, %%eax\n" 544 "movl %%eax, %%cr0\n" 545 /* Disable pae */ 546 "movl %%cr4, %%eax\n" 547 "andl $0xffffffdf, %%eax\n" 548 "movl %%eax, %%cr4\n" 549 : 550 : 551 : "eax"); 552 } 553 554 static bool can_detect_long_mode(void) 555 { 556 return cpuid_eax(0x80000000) > 0x80000000UL; 557 } 558 559 static bool has_long_mode(void) 560 { 561 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 562 } 563 564 int cpu_has_64bit(void) 565 { 566 return has_cpuid() && can_detect_long_mode() && 567 has_long_mode(); 568 } 569 570 const char *cpu_vendor_name(int vendor) 571 { 572 const char *name; 573 name = "<invalid cpu vendor>"; 574 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 575 (x86_vendor_name[vendor] != 0)) 576 name = x86_vendor_name[vendor]; 577 578 return name; 579 } 580 581 char *cpu_get_name(char *name) 582 { 583 unsigned int *name_as_ints = (unsigned int *)name; 584 struct cpuid_result regs; 585 char *ptr; 586 int i; 587 588 /* This bit adds up to 48 bytes */ 589 for (i = 0; i < 3; i++) { 590 regs = cpuid(0x80000002 + i); 591 name_as_ints[i * 4 + 0] = regs.eax; 592 name_as_ints[i * 4 + 1] = regs.ebx; 593 name_as_ints[i * 4 + 2] = regs.ecx; 594 name_as_ints[i * 4 + 3] = regs.edx; 595 } 596 name[CPU_MAX_NAME_LEN - 1] = '\0'; 597 598 /* Skip leading spaces. */ 599 ptr = name; 600 while (*ptr == ' ') 601 ptr++; 602 603 return ptr; 604 } 605 606 int default_print_cpuinfo(void) 607 { 608 printf("CPU: %s, vendor %s, device %xh\n", 609 cpu_has_64bit() ? "x86_64" : "x86", 610 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 611 612 return 0; 613 } 614 615 #define PAGETABLE_SIZE (6 * 4096) 616 617 /** 618 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 619 * 620 * @pgtable: Pointer to a 24iKB block of memory 621 */ 622 static void build_pagetable(uint32_t *pgtable) 623 { 624 uint i; 625 626 memset(pgtable, '\0', PAGETABLE_SIZE); 627 628 /* Level 4 needs a single entry */ 629 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 630 631 /* Level 3 has one 64-bit entry for each GiB of memory */ 632 for (i = 0; i < 4; i++) { 633 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 634 0x1000 * i + 7; 635 } 636 637 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 638 for (i = 0; i < 2048; i++) 639 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 640 } 641 642 int cpu_jump_to_64bit(ulong setup_base, ulong target) 643 { 644 uint32_t *pgtable; 645 646 pgtable = memalign(4096, PAGETABLE_SIZE); 647 if (!pgtable) 648 return -ENOMEM; 649 650 build_pagetable(pgtable); 651 cpu_call64((ulong)pgtable, setup_base, target); 652 free(pgtable); 653 654 return -EFAULT; 655 } 656 657 void show_boot_progress(int val) 658 { 659 outb(val, POST_PORT); 660 } 661 662 #ifndef CONFIG_SYS_COREBOOT 663 int last_stage_init(void) 664 { 665 write_tables(); 666 667 return 0; 668 } 669 #endif 670 671 #ifdef CONFIG_SMP 672 static int enable_smis(struct udevice *cpu, void *unused) 673 { 674 return 0; 675 } 676 677 static struct mp_flight_record mp_steps[] = { 678 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), 679 /* Wait for APs to finish initialization before proceeding */ 680 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), 681 }; 682 683 static int x86_mp_init(void) 684 { 685 struct mp_params mp_params; 686 687 mp_params.parallel_microcode_load = 0, 688 mp_params.flight_plan = &mp_steps[0]; 689 mp_params.num_records = ARRAY_SIZE(mp_steps); 690 mp_params.microcode_pointer = 0; 691 692 if (mp_init(&mp_params)) { 693 printf("Warning: MP init failure\n"); 694 return -EIO; 695 } 696 697 return 0; 698 } 699 #endif 700 701 static int x86_init_cpus(void) 702 { 703 #ifdef CONFIG_SMP 704 debug("Init additional CPUs\n"); 705 x86_mp_init(); 706 #else 707 struct udevice *dev; 708 709 /* 710 * This causes the cpu-x86 driver to be probed. 711 * We don't check return value here as we want to allow boards 712 * which have not been converted to use cpu uclass driver to boot. 713 */ 714 uclass_first_device(UCLASS_CPU, &dev); 715 #endif 716 717 return 0; 718 } 719 720 int cpu_init_r(void) 721 { 722 struct udevice *dev; 723 int ret; 724 725 if (!ll_boot_init()) 726 return 0; 727 728 ret = x86_init_cpus(); 729 if (ret) 730 return ret; 731 732 /* 733 * Set up the northbridge, PCH and LPC if available. Note that these 734 * may have had some limited pre-relocation init if they were probed 735 * before relocation, but this is post relocation. 736 */ 737 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 738 uclass_first_device(UCLASS_PCH, &dev); 739 uclass_first_device(UCLASS_LPC, &dev); 740 741 return 0; 742 } 743