1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <errno.h> 22 #include <malloc.h> 23 #include <asm/control_regs.h> 24 #include <asm/cpu.h> 25 #include <asm/processor.h> 26 #include <asm/processor-flags.h> 27 #include <asm/interrupt.h> 28 #include <linux/compiler.h> 29 30 /* 31 * Constructor for a conventional segment GDT (or LDT) entry 32 * This is a macro so it can be used in initialisers 33 */ 34 #define GDT_ENTRY(flags, base, limit) \ 35 ((((base) & 0xff000000ULL) << (56-24)) | \ 36 (((flags) & 0x0000f0ffULL) << 40) | \ 37 (((limit) & 0x000f0000ULL) << (48-16)) | \ 38 (((base) & 0x00ffffffULL) << 16) | \ 39 (((limit) & 0x0000ffffULL))) 40 41 struct gdt_ptr { 42 u16 len; 43 u32 ptr; 44 } __packed; 45 46 static void load_ds(u32 segment) 47 { 48 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 49 } 50 51 static void load_es(u32 segment) 52 { 53 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 54 } 55 56 static void load_fs(u32 segment) 57 { 58 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 59 } 60 61 static void load_gs(u32 segment) 62 { 63 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 64 } 65 66 static void load_ss(u32 segment) 67 { 68 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 69 } 70 71 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 72 { 73 struct gdt_ptr gdt; 74 75 gdt.len = (num_entries * 8) - 1; 76 gdt.ptr = (u32)boot_gdt; 77 78 asm volatile("lgdtl %0\n" : : "m" (gdt)); 79 } 80 81 void setup_gdt(gd_t *id, u64 *gdt_addr) 82 { 83 /* CS: code, read/execute, 4 GB, base 0 */ 84 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 85 86 /* DS: data, read/write, 4 GB, base 0 */ 87 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 88 89 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 90 id->arch.gd_addr = id; 91 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 92 (ulong)&id->arch.gd_addr, 0xfffff); 93 94 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 95 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); 96 97 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 98 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); 99 100 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 101 load_ds(X86_GDT_ENTRY_32BIT_DS); 102 load_es(X86_GDT_ENTRY_32BIT_DS); 103 load_gs(X86_GDT_ENTRY_32BIT_DS); 104 load_ss(X86_GDT_ENTRY_32BIT_DS); 105 load_fs(X86_GDT_ENTRY_32BIT_FS); 106 } 107 108 int __weak x86_cleanup_before_linux(void) 109 { 110 #ifdef CONFIG_BOOTSTAGE_STASH 111 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, 112 CONFIG_BOOTSTAGE_STASH_SIZE); 113 #endif 114 115 return 0; 116 } 117 118 int x86_cpu_init_f(void) 119 { 120 const u32 em_rst = ~X86_CR0_EM; 121 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 122 123 /* initialize FPU, reset EM, set MP and NE */ 124 asm ("fninit\n" \ 125 "movl %%cr0, %%eax\n" \ 126 "andl %0, %%eax\n" \ 127 "orl %1, %%eax\n" \ 128 "movl %%eax, %%cr0\n" \ 129 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 130 131 return 0; 132 } 133 134 int x86_cpu_init_r(void) 135 { 136 /* Initialize core interrupt and exception functionality of CPU */ 137 cpu_init_interrupts(); 138 return 0; 139 } 140 int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); 141 142 void x86_enable_caches(void) 143 { 144 unsigned long cr0; 145 146 cr0 = read_cr0(); 147 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 148 write_cr0(cr0); 149 wbinvd(); 150 } 151 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 152 153 void x86_disable_caches(void) 154 { 155 unsigned long cr0; 156 157 cr0 = read_cr0(); 158 cr0 |= X86_CR0_NW | X86_CR0_CD; 159 wbinvd(); 160 write_cr0(cr0); 161 wbinvd(); 162 } 163 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 164 165 int x86_init_cache(void) 166 { 167 enable_caches(); 168 169 return 0; 170 } 171 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 172 173 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 174 { 175 printf("resetting ...\n"); 176 177 /* wait 50 ms */ 178 udelay(50000); 179 disable_interrupts(); 180 reset_cpu(0); 181 182 /*NOTREACHED*/ 183 return 0; 184 } 185 186 void flush_cache(unsigned long dummy1, unsigned long dummy2) 187 { 188 asm("wbinvd\n"); 189 } 190 191 void __attribute__ ((regparm(0))) generate_gpf(void); 192 193 /* segment 0x70 is an arbitrary segment which does not exist */ 194 asm(".globl generate_gpf\n" 195 ".hidden generate_gpf\n" 196 ".type generate_gpf, @function\n" 197 "generate_gpf:\n" 198 "ljmp $0x70, $0x47114711\n"); 199 200 void __reset_cpu(ulong addr) 201 { 202 printf("Resetting using x86 Triple Fault\n"); 203 set_vector(13, generate_gpf); /* general protection fault handler */ 204 set_vector(8, generate_gpf); /* double fault handler */ 205 generate_gpf(); /* start the show */ 206 } 207 void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); 208 209 int dcache_status(void) 210 { 211 return !(read_cr0() & 0x40000000); 212 } 213 214 /* Define these functions to allow ehch-hcd to function */ 215 void flush_dcache_range(unsigned long start, unsigned long stop) 216 { 217 } 218 219 void invalidate_dcache_range(unsigned long start, unsigned long stop) 220 { 221 } 222 223 void dcache_enable(void) 224 { 225 enable_caches(); 226 } 227 228 void dcache_disable(void) 229 { 230 disable_caches(); 231 } 232 233 void icache_enable(void) 234 { 235 } 236 237 void icache_disable(void) 238 { 239 } 240 241 int icache_status(void) 242 { 243 return 1; 244 } 245 246 void cpu_enable_paging_pae(ulong cr3) 247 { 248 __asm__ __volatile__( 249 /* Load the page table address */ 250 "movl %0, %%cr3\n" 251 /* Enable pae */ 252 "movl %%cr4, %%eax\n" 253 "orl $0x00000020, %%eax\n" 254 "movl %%eax, %%cr4\n" 255 /* Enable paging */ 256 "movl %%cr0, %%eax\n" 257 "orl $0x80000000, %%eax\n" 258 "movl %%eax, %%cr0\n" 259 : 260 : "r" (cr3) 261 : "eax"); 262 } 263 264 void cpu_disable_paging_pae(void) 265 { 266 /* Turn off paging */ 267 __asm__ __volatile__ ( 268 /* Disable paging */ 269 "movl %%cr0, %%eax\n" 270 "andl $0x7fffffff, %%eax\n" 271 "movl %%eax, %%cr0\n" 272 /* Disable pae */ 273 "movl %%cr4, %%eax\n" 274 "andl $0xffffffdf, %%eax\n" 275 "movl %%eax, %%cr4\n" 276 : 277 : 278 : "eax"); 279 } 280 281 static bool has_cpuid(void) 282 { 283 unsigned long flag; 284 285 asm volatile("pushf\n" \ 286 "pop %%eax\n" 287 "mov %%eax, %%ecx\n" /* ecx = flags */ 288 "xor %1, %%eax\n" 289 "push %%eax\n" 290 "popf\n" /* flags ^= $2 */ 291 "pushf\n" 292 "pop %%eax\n" /* eax = flags */ 293 "push %%ecx\n" 294 "popf\n" /* flags = ecx */ 295 "xor %%ecx, %%eax\n" 296 "mov %%eax, %0" 297 : "=r" (flag) 298 : "i" (1 << 21) 299 : "eax", "ecx", "memory"); 300 301 return flag != 0; 302 } 303 304 static bool can_detect_long_mode(void) 305 { 306 unsigned long flag; 307 308 asm volatile("mov $0x80000000, %%eax\n" 309 "cpuid\n" 310 "mov %%eax, %0" 311 : "=r" (flag) 312 : 313 : "eax", "ebx", "ecx", "edx", "memory"); 314 315 return flag > 0x80000000UL; 316 } 317 318 static bool has_long_mode(void) 319 { 320 unsigned long flag; 321 322 asm volatile("mov $0x80000001, %%eax\n" 323 "cpuid\n" 324 "mov %%edx, %0" 325 : "=r" (flag) 326 : 327 : "eax", "ebx", "ecx", "edx", "memory"); 328 329 return flag & (1 << 29) ? true : false; 330 } 331 332 int cpu_has_64bit(void) 333 { 334 return has_cpuid() && can_detect_long_mode() && 335 has_long_mode(); 336 } 337 338 int print_cpuinfo(void) 339 { 340 printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86"); 341 342 return 0; 343 } 344 345 #define PAGETABLE_SIZE (6 * 4096) 346 347 /** 348 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 349 * 350 * @pgtable: Pointer to a 24iKB block of memory 351 */ 352 static void build_pagetable(uint32_t *pgtable) 353 { 354 uint i; 355 356 memset(pgtable, '\0', PAGETABLE_SIZE); 357 358 /* Level 4 needs a single entry */ 359 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 360 361 /* Level 3 has one 64-bit entry for each GiB of memory */ 362 for (i = 0; i < 4; i++) { 363 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 364 0x1000 * i + 7; 365 } 366 367 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 368 for (i = 0; i < 2048; i++) 369 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 370 } 371 372 int cpu_jump_to_64bit(ulong setup_base, ulong target) 373 { 374 uint32_t *pgtable; 375 376 pgtable = memalign(4096, PAGETABLE_SIZE); 377 if (!pgtable) 378 return -ENOMEM; 379 380 build_pagetable(pgtable); 381 cpu_call64((ulong)pgtable, setup_base, target); 382 free(pgtable); 383 384 return -EFAULT; 385 } 386