xref: /rk3399_rockchip-uboot/arch/x86/cpu/cpu.c (revision 52845296be8190c3f581090d6336fa033f2bd2d8) 
1 /*
2  * (C) Copyright 2008-2011
3  * Graeme Russ, <graeme.russ@gmail.com>
4  *
5  * (C) Copyright 2002
6  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7  *
8  * (C) Copyright 2002
9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10  * Marius Groeger <mgroeger@sysgo.de>
11  *
12  * (C) Copyright 2002
13  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14  * Alex Zuepke <azu@sysgo.de>
15  *
16  * Part of this file is adapted from coreboot
17  * src/arch/x86/lib/cpu.c
18  *
19  * SPDX-License-Identifier:	GPL-2.0+
20  */
21 
22 #include <common.h>
23 #include <command.h>
24 #include <errno.h>
25 #include <malloc.h>
26 #include <asm/control_regs.h>
27 #include <asm/cpu.h>
28 #include <asm/post.h>
29 #include <asm/processor.h>
30 #include <asm/processor-flags.h>
31 #include <asm/interrupt.h>
32 #include <asm/tables.h>
33 #include <linux/compiler.h>
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 /*
38  * Constructor for a conventional segment GDT (or LDT) entry
39  * This is a macro so it can be used in initialisers
40  */
41 #define GDT_ENTRY(flags, base, limit)			\
42 	((((base)  & 0xff000000ULL) << (56-24)) |	\
43 	 (((flags) & 0x0000f0ffULL) << 40) |		\
44 	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
45 	 (((base)  & 0x00ffffffULL) << 16) |		\
46 	 (((limit) & 0x0000ffffULL)))
47 
48 struct gdt_ptr {
49 	u16 len;
50 	u32 ptr;
51 } __packed;
52 
53 struct cpu_device_id {
54 	unsigned vendor;
55 	unsigned device;
56 };
57 
58 struct cpuinfo_x86 {
59 	uint8_t x86;            /* CPU family */
60 	uint8_t x86_vendor;     /* CPU vendor */
61 	uint8_t x86_model;
62 	uint8_t x86_mask;
63 };
64 
65 /*
66  * List of cpu vendor strings along with their normalized
67  * id values.
68  */
69 static struct {
70 	int vendor;
71 	const char *name;
72 } x86_vendors[] = {
73 	{ X86_VENDOR_INTEL,     "GenuineIntel", },
74 	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
75 	{ X86_VENDOR_AMD,       "AuthenticAMD", },
76 	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
77 	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
78 	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
79 	{ X86_VENDOR_RISE,      "RiseRiseRise", },
80 	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
81 	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
82 	{ X86_VENDOR_NSC,       "Geode by NSC", },
83 	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
84 };
85 
86 static const char *const x86_vendor_name[] = {
87 	[X86_VENDOR_INTEL]     = "Intel",
88 	[X86_VENDOR_CYRIX]     = "Cyrix",
89 	[X86_VENDOR_AMD]       = "AMD",
90 	[X86_VENDOR_UMC]       = "UMC",
91 	[X86_VENDOR_NEXGEN]    = "NexGen",
92 	[X86_VENDOR_CENTAUR]   = "Centaur",
93 	[X86_VENDOR_RISE]      = "Rise",
94 	[X86_VENDOR_TRANSMETA] = "Transmeta",
95 	[X86_VENDOR_NSC]       = "NSC",
96 	[X86_VENDOR_SIS]       = "SiS",
97 };
98 
99 static void load_ds(u32 segment)
100 {
101 	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
102 }
103 
104 static void load_es(u32 segment)
105 {
106 	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
107 }
108 
109 static void load_fs(u32 segment)
110 {
111 	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
112 }
113 
114 static void load_gs(u32 segment)
115 {
116 	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
117 }
118 
119 static void load_ss(u32 segment)
120 {
121 	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
122 }
123 
124 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
125 {
126 	struct gdt_ptr gdt;
127 
128 	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
129 	gdt.ptr = (u32)boot_gdt;
130 
131 	asm volatile("lgdtl %0\n" : : "m" (gdt));
132 }
133 
134 void setup_gdt(gd_t *id, u64 *gdt_addr)
135 {
136 	id->arch.gdt = gdt_addr;
137 	/* CS: code, read/execute, 4 GB, base 0 */
138 	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
139 
140 	/* DS: data, read/write, 4 GB, base 0 */
141 	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
142 
143 	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
144 	id->arch.gd_addr = id;
145 	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
146 		     (ulong)&id->arch.gd_addr, 0xfffff);
147 
148 	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
149 	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
150 
151 	/* 16-bit DS: data, read/write, 64 kB, base 0 */
152 	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
153 
154 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
155 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
156 
157 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
158 	load_ds(X86_GDT_ENTRY_32BIT_DS);
159 	load_es(X86_GDT_ENTRY_32BIT_DS);
160 	load_gs(X86_GDT_ENTRY_32BIT_DS);
161 	load_ss(X86_GDT_ENTRY_32BIT_DS);
162 	load_fs(X86_GDT_ENTRY_32BIT_FS);
163 }
164 
165 int __weak x86_cleanup_before_linux(void)
166 {
167 #ifdef CONFIG_BOOTSTAGE_STASH
168 	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
169 			CONFIG_BOOTSTAGE_STASH_SIZE);
170 #endif
171 
172 	return 0;
173 }
174 
175 /*
176  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
177  * by the fact that they preserve the flags across the division of 5/2.
178  * PII and PPro exhibit this behavior too, but they have cpuid available.
179  */
180 
181 /*
182  * Perform the Cyrix 5/2 test. A Cyrix won't change
183  * the flags, while other 486 chips will.
184  */
185 static inline int test_cyrix_52div(void)
186 {
187 	unsigned int test;
188 
189 	__asm__ __volatile__(
190 	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
191 	     "div %b2\n\t"	/* divide 5 by 2 */
192 	     "lahf"		/* store flags into %ah */
193 	     : "=a" (test)
194 	     : "0" (5), "q" (2)
195 	     : "cc");
196 
197 	/* AH is 0x02 on Cyrix after the divide.. */
198 	return (unsigned char) (test >> 8) == 0x02;
199 }
200 
201 /*
202  *	Detect a NexGen CPU running without BIOS hypercode new enough
203  *	to have CPUID. (Thanks to Herbert Oppmann)
204  */
205 
206 static int deep_magic_nexgen_probe(void)
207 {
208 	int ret;
209 
210 	__asm__ __volatile__ (
211 		"	movw	$0x5555, %%ax\n"
212 		"	xorw	%%dx,%%dx\n"
213 		"	movw	$2, %%cx\n"
214 		"	divw	%%cx\n"
215 		"	movl	$0, %%eax\n"
216 		"	jnz	1f\n"
217 		"	movl	$1, %%eax\n"
218 		"1:\n"
219 		: "=a" (ret) : : "cx", "dx");
220 	return  ret;
221 }
222 
223 static bool has_cpuid(void)
224 {
225 	return flag_is_changeable_p(X86_EFLAGS_ID);
226 }
227 
228 static bool has_mtrr(void)
229 {
230 	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
231 }
232 
233 static int build_vendor_name(char *vendor_name)
234 {
235 	struct cpuid_result result;
236 	result = cpuid(0x00000000);
237 	unsigned int *name_as_ints = (unsigned int *)vendor_name;
238 
239 	name_as_ints[0] = result.ebx;
240 	name_as_ints[1] = result.edx;
241 	name_as_ints[2] = result.ecx;
242 
243 	return result.eax;
244 }
245 
246 static void identify_cpu(struct cpu_device_id *cpu)
247 {
248 	char vendor_name[16];
249 	int i;
250 
251 	vendor_name[0] = '\0'; /* Unset */
252 	cpu->device = 0; /* fix gcc 4.4.4 warning */
253 
254 	/* Find the id and vendor_name */
255 	if (!has_cpuid()) {
256 		/* Its a 486 if we can modify the AC flag */
257 		if (flag_is_changeable_p(X86_EFLAGS_AC))
258 			cpu->device = 0x00000400; /* 486 */
259 		else
260 			cpu->device = 0x00000300; /* 386 */
261 		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
262 			memcpy(vendor_name, "CyrixInstead", 13);
263 			/* If we ever care we can enable cpuid here */
264 		}
265 		/* Detect NexGen with old hypercode */
266 		else if (deep_magic_nexgen_probe())
267 			memcpy(vendor_name, "NexGenDriven", 13);
268 	}
269 	if (has_cpuid()) {
270 		int  cpuid_level;
271 
272 		cpuid_level = build_vendor_name(vendor_name);
273 		vendor_name[12] = '\0';
274 
275 		/* Intel-defined flags: level 0x00000001 */
276 		if (cpuid_level >= 0x00000001) {
277 			cpu->device = cpuid_eax(0x00000001);
278 		} else {
279 			/* Have CPUID level 0 only unheard of */
280 			cpu->device = 0x00000400;
281 		}
282 	}
283 	cpu->vendor = X86_VENDOR_UNKNOWN;
284 	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
285 		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
286 			cpu->vendor = x86_vendors[i].vendor;
287 			break;
288 		}
289 	}
290 }
291 
292 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
293 {
294 	c->x86 = (tfms >> 8) & 0xf;
295 	c->x86_model = (tfms >> 4) & 0xf;
296 	c->x86_mask = tfms & 0xf;
297 	if (c->x86 == 0xf)
298 		c->x86 += (tfms >> 20) & 0xff;
299 	if (c->x86 >= 0x6)
300 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
301 }
302 
303 int x86_cpu_init_f(void)
304 {
305 	const u32 em_rst = ~X86_CR0_EM;
306 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
307 
308 	/* initialize FPU, reset EM, set MP and NE */
309 	asm ("fninit\n" \
310 	     "movl %%cr0, %%eax\n" \
311 	     "andl %0, %%eax\n" \
312 	     "orl  %1, %%eax\n" \
313 	     "movl %%eax, %%cr0\n" \
314 	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
315 
316 	/* identify CPU via cpuid and store the decoded info into gd->arch */
317 	if (has_cpuid()) {
318 		struct cpu_device_id cpu;
319 		struct cpuinfo_x86 c;
320 
321 		identify_cpu(&cpu);
322 		get_fms(&c, cpu.device);
323 		gd->arch.x86 = c.x86;
324 		gd->arch.x86_vendor = cpu.vendor;
325 		gd->arch.x86_model = c.x86_model;
326 		gd->arch.x86_mask = c.x86_mask;
327 		gd->arch.x86_device = cpu.device;
328 
329 		gd->arch.has_mtrr = has_mtrr();
330 	}
331 
332 	return 0;
333 }
334 
335 void x86_enable_caches(void)
336 {
337 	unsigned long cr0;
338 
339 	cr0 = read_cr0();
340 	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
341 	write_cr0(cr0);
342 	wbinvd();
343 }
344 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
345 
346 void x86_disable_caches(void)
347 {
348 	unsigned long cr0;
349 
350 	cr0 = read_cr0();
351 	cr0 |= X86_CR0_NW | X86_CR0_CD;
352 	wbinvd();
353 	write_cr0(cr0);
354 	wbinvd();
355 }
356 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
357 
358 int x86_init_cache(void)
359 {
360 	enable_caches();
361 
362 	return 0;
363 }
364 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
365 
366 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
367 {
368 	printf("resetting ...\n");
369 
370 	/* wait 50 ms */
371 	udelay(50000);
372 	disable_interrupts();
373 	reset_cpu(0);
374 
375 	/*NOTREACHED*/
376 	return 0;
377 }
378 
379 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
380 {
381 	asm("wbinvd\n");
382 }
383 
384 __weak void reset_cpu(ulong addr)
385 {
386 	/* Do a hard reset through the chipset's reset control register */
387 	outb(SYS_RST | RST_CPU, PORT_RESET);
388 	for (;;)
389 		cpu_hlt();
390 }
391 
392 void x86_full_reset(void)
393 {
394 	outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
395 }
396 
397 int dcache_status(void)
398 {
399 	return !(read_cr0() & 0x40000000);
400 }
401 
402 /* Define these functions to allow ehch-hcd to function */
403 void flush_dcache_range(unsigned long start, unsigned long stop)
404 {
405 }
406 
407 void invalidate_dcache_range(unsigned long start, unsigned long stop)
408 {
409 }
410 
411 void dcache_enable(void)
412 {
413 	enable_caches();
414 }
415 
416 void dcache_disable(void)
417 {
418 	disable_caches();
419 }
420 
421 void icache_enable(void)
422 {
423 }
424 
425 void icache_disable(void)
426 {
427 }
428 
429 int icache_status(void)
430 {
431 	return 1;
432 }
433 
434 void cpu_enable_paging_pae(ulong cr3)
435 {
436 	__asm__ __volatile__(
437 		/* Load the page table address */
438 		"movl	%0, %%cr3\n"
439 		/* Enable pae */
440 		"movl	%%cr4, %%eax\n"
441 		"orl	$0x00000020, %%eax\n"
442 		"movl	%%eax, %%cr4\n"
443 		/* Enable paging */
444 		"movl	%%cr0, %%eax\n"
445 		"orl	$0x80000000, %%eax\n"
446 		"movl	%%eax, %%cr0\n"
447 		:
448 		: "r" (cr3)
449 		: "eax");
450 }
451 
452 void cpu_disable_paging_pae(void)
453 {
454 	/* Turn off paging */
455 	__asm__ __volatile__ (
456 		/* Disable paging */
457 		"movl	%%cr0, %%eax\n"
458 		"andl	$0x7fffffff, %%eax\n"
459 		"movl	%%eax, %%cr0\n"
460 		/* Disable pae */
461 		"movl	%%cr4, %%eax\n"
462 		"andl	$0xffffffdf, %%eax\n"
463 		"movl	%%eax, %%cr4\n"
464 		:
465 		:
466 		: "eax");
467 }
468 
469 static bool can_detect_long_mode(void)
470 {
471 	return cpuid_eax(0x80000000) > 0x80000000UL;
472 }
473 
474 static bool has_long_mode(void)
475 {
476 	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
477 }
478 
479 int cpu_has_64bit(void)
480 {
481 	return has_cpuid() && can_detect_long_mode() &&
482 		has_long_mode();
483 }
484 
485 const char *cpu_vendor_name(int vendor)
486 {
487 	const char *name;
488 	name = "<invalid cpu vendor>";
489 	if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
490 	    (x86_vendor_name[vendor] != 0))
491 		name = x86_vendor_name[vendor];
492 
493 	return name;
494 }
495 
496 char *cpu_get_name(char *name)
497 {
498 	unsigned int *name_as_ints = (unsigned int *)name;
499 	struct cpuid_result regs;
500 	char *ptr;
501 	int i;
502 
503 	/* This bit adds up to 48 bytes */
504 	for (i = 0; i < 3; i++) {
505 		regs = cpuid(0x80000002 + i);
506 		name_as_ints[i * 4 + 0] = regs.eax;
507 		name_as_ints[i * 4 + 1] = regs.ebx;
508 		name_as_ints[i * 4 + 2] = regs.ecx;
509 		name_as_ints[i * 4 + 3] = regs.edx;
510 	}
511 	name[CPU_MAX_NAME_LEN - 1] = '\0';
512 
513 	/* Skip leading spaces. */
514 	ptr = name;
515 	while (*ptr == ' ')
516 		ptr++;
517 
518 	return ptr;
519 }
520 
521 int default_print_cpuinfo(void)
522 {
523 	printf("CPU: %s, vendor %s, device %xh\n",
524 	       cpu_has_64bit() ? "x86_64" : "x86",
525 	       cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
526 
527 	return 0;
528 }
529 
530 #define PAGETABLE_SIZE		(6 * 4096)
531 
532 /**
533  * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
534  *
535  * @pgtable: Pointer to a 24iKB block of memory
536  */
537 static void build_pagetable(uint32_t *pgtable)
538 {
539 	uint i;
540 
541 	memset(pgtable, '\0', PAGETABLE_SIZE);
542 
543 	/* Level 4 needs a single entry */
544 	pgtable[0] = (uint32_t)&pgtable[1024] + 7;
545 
546 	/* Level 3 has one 64-bit entry for each GiB of memory */
547 	for (i = 0; i < 4; i++) {
548 		pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
549 							0x1000 * i + 7;
550 	}
551 
552 	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
553 	for (i = 0; i < 2048; i++)
554 		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
555 }
556 
557 int cpu_jump_to_64bit(ulong setup_base, ulong target)
558 {
559 	uint32_t *pgtable;
560 
561 	pgtable = memalign(4096, PAGETABLE_SIZE);
562 	if (!pgtable)
563 		return -ENOMEM;
564 
565 	build_pagetable(pgtable);
566 	cpu_call64((ulong)pgtable, setup_base, target);
567 	free(pgtable);
568 
569 	return -EFAULT;
570 }
571 
572 void show_boot_progress(int val)
573 {
574 #if MIN_PORT80_KCLOCKS_DELAY
575 	/*
576 	 * Scale the time counter reading to avoid using 64 bit arithmetics.
577 	 * Can't use get_timer() here becuase it could be not yet
578 	 * initialized or even implemented.
579 	 */
580 	if (!gd->arch.tsc_prev) {
581 		gd->arch.tsc_base_kclocks = rdtsc() / 1000;
582 		gd->arch.tsc_prev = 0;
583 	} else {
584 		uint32_t now;
585 
586 		do {
587 			now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
588 		} while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
589 		gd->arch.tsc_prev = now;
590 	}
591 #endif
592 	outb(val, POST_PORT);
593 }
594 
595 #ifndef CONFIG_SYS_COREBOOT
596 int last_stage_init(void)
597 {
598 	write_tables();
599 
600 	return 0;
601 }
602 #endif
603