1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <errno.h> 25 #include <malloc.h> 26 #include <asm/control_regs.h> 27 #include <asm/cpu.h> 28 #include <asm/post.h> 29 #include <asm/processor.h> 30 #include <asm/processor-flags.h> 31 #include <asm/interrupt.h> 32 #include <asm/tables.h> 33 #include <linux/compiler.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* 38 * Constructor for a conventional segment GDT (or LDT) entry 39 * This is a macro so it can be used in initialisers 40 */ 41 #define GDT_ENTRY(flags, base, limit) \ 42 ((((base) & 0xff000000ULL) << (56-24)) | \ 43 (((flags) & 0x0000f0ffULL) << 40) | \ 44 (((limit) & 0x000f0000ULL) << (48-16)) | \ 45 (((base) & 0x00ffffffULL) << 16) | \ 46 (((limit) & 0x0000ffffULL))) 47 48 struct gdt_ptr { 49 u16 len; 50 u32 ptr; 51 } __packed; 52 53 struct cpu_device_id { 54 unsigned vendor; 55 unsigned device; 56 }; 57 58 struct cpuinfo_x86 { 59 uint8_t x86; /* CPU family */ 60 uint8_t x86_vendor; /* CPU vendor */ 61 uint8_t x86_model; 62 uint8_t x86_mask; 63 }; 64 65 /* 66 * List of cpu vendor strings along with their normalized 67 * id values. 68 */ 69 static struct { 70 int vendor; 71 const char *name; 72 } x86_vendors[] = { 73 { X86_VENDOR_INTEL, "GenuineIntel", }, 74 { X86_VENDOR_CYRIX, "CyrixInstead", }, 75 { X86_VENDOR_AMD, "AuthenticAMD", }, 76 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 77 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 78 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 79 { X86_VENDOR_RISE, "RiseRiseRise", }, 80 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 81 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 82 { X86_VENDOR_NSC, "Geode by NSC", }, 83 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 84 }; 85 86 static const char *const x86_vendor_name[] = { 87 [X86_VENDOR_INTEL] = "Intel", 88 [X86_VENDOR_CYRIX] = "Cyrix", 89 [X86_VENDOR_AMD] = "AMD", 90 [X86_VENDOR_UMC] = "UMC", 91 [X86_VENDOR_NEXGEN] = "NexGen", 92 [X86_VENDOR_CENTAUR] = "Centaur", 93 [X86_VENDOR_RISE] = "Rise", 94 [X86_VENDOR_TRANSMETA] = "Transmeta", 95 [X86_VENDOR_NSC] = "NSC", 96 [X86_VENDOR_SIS] = "SiS", 97 }; 98 99 static void load_ds(u32 segment) 100 { 101 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 102 } 103 104 static void load_es(u32 segment) 105 { 106 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 107 } 108 109 static void load_fs(u32 segment) 110 { 111 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 112 } 113 114 static void load_gs(u32 segment) 115 { 116 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 117 } 118 119 static void load_ss(u32 segment) 120 { 121 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 122 } 123 124 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 125 { 126 struct gdt_ptr gdt; 127 128 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 129 gdt.ptr = (u32)boot_gdt; 130 131 asm volatile("lgdtl %0\n" : : "m" (gdt)); 132 } 133 134 void setup_gdt(gd_t *id, u64 *gdt_addr) 135 { 136 /* CS: code, read/execute, 4 GB, base 0 */ 137 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 138 139 /* DS: data, read/write, 4 GB, base 0 */ 140 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 141 142 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 143 id->arch.gd_addr = id; 144 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 145 (ulong)&id->arch.gd_addr, 0xfffff); 146 147 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 148 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 149 150 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 151 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 152 153 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 154 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 155 156 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 157 load_ds(X86_GDT_ENTRY_32BIT_DS); 158 load_es(X86_GDT_ENTRY_32BIT_DS); 159 load_gs(X86_GDT_ENTRY_32BIT_DS); 160 load_ss(X86_GDT_ENTRY_32BIT_DS); 161 load_fs(X86_GDT_ENTRY_32BIT_FS); 162 } 163 164 int __weak x86_cleanup_before_linux(void) 165 { 166 #ifdef CONFIG_BOOTSTAGE_STASH 167 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 168 CONFIG_BOOTSTAGE_STASH_SIZE); 169 #endif 170 171 return 0; 172 } 173 174 /* 175 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 176 * by the fact that they preserve the flags across the division of 5/2. 177 * PII and PPro exhibit this behavior too, but they have cpuid available. 178 */ 179 180 /* 181 * Perform the Cyrix 5/2 test. A Cyrix won't change 182 * the flags, while other 486 chips will. 183 */ 184 static inline int test_cyrix_52div(void) 185 { 186 unsigned int test; 187 188 __asm__ __volatile__( 189 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 190 "div %b2\n\t" /* divide 5 by 2 */ 191 "lahf" /* store flags into %ah */ 192 : "=a" (test) 193 : "0" (5), "q" (2) 194 : "cc"); 195 196 /* AH is 0x02 on Cyrix after the divide.. */ 197 return (unsigned char) (test >> 8) == 0x02; 198 } 199 200 /* 201 * Detect a NexGen CPU running without BIOS hypercode new enough 202 * to have CPUID. (Thanks to Herbert Oppmann) 203 */ 204 205 static int deep_magic_nexgen_probe(void) 206 { 207 int ret; 208 209 __asm__ __volatile__ ( 210 " movw $0x5555, %%ax\n" 211 " xorw %%dx,%%dx\n" 212 " movw $2, %%cx\n" 213 " divw %%cx\n" 214 " movl $0, %%eax\n" 215 " jnz 1f\n" 216 " movl $1, %%eax\n" 217 "1:\n" 218 : "=a" (ret) : : "cx", "dx"); 219 return ret; 220 } 221 222 static bool has_cpuid(void) 223 { 224 return flag_is_changeable_p(X86_EFLAGS_ID); 225 } 226 227 static bool has_mtrr(void) 228 { 229 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 230 } 231 232 static int build_vendor_name(char *vendor_name) 233 { 234 struct cpuid_result result; 235 result = cpuid(0x00000000); 236 unsigned int *name_as_ints = (unsigned int *)vendor_name; 237 238 name_as_ints[0] = result.ebx; 239 name_as_ints[1] = result.edx; 240 name_as_ints[2] = result.ecx; 241 242 return result.eax; 243 } 244 245 static void identify_cpu(struct cpu_device_id *cpu) 246 { 247 char vendor_name[16]; 248 int i; 249 250 vendor_name[0] = '\0'; /* Unset */ 251 cpu->device = 0; /* fix gcc 4.4.4 warning */ 252 253 /* Find the id and vendor_name */ 254 if (!has_cpuid()) { 255 /* Its a 486 if we can modify the AC flag */ 256 if (flag_is_changeable_p(X86_EFLAGS_AC)) 257 cpu->device = 0x00000400; /* 486 */ 258 else 259 cpu->device = 0x00000300; /* 386 */ 260 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 261 memcpy(vendor_name, "CyrixInstead", 13); 262 /* If we ever care we can enable cpuid here */ 263 } 264 /* Detect NexGen with old hypercode */ 265 else if (deep_magic_nexgen_probe()) 266 memcpy(vendor_name, "NexGenDriven", 13); 267 } 268 if (has_cpuid()) { 269 int cpuid_level; 270 271 cpuid_level = build_vendor_name(vendor_name); 272 vendor_name[12] = '\0'; 273 274 /* Intel-defined flags: level 0x00000001 */ 275 if (cpuid_level >= 0x00000001) { 276 cpu->device = cpuid_eax(0x00000001); 277 } else { 278 /* Have CPUID level 0 only unheard of */ 279 cpu->device = 0x00000400; 280 } 281 } 282 cpu->vendor = X86_VENDOR_UNKNOWN; 283 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 284 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 285 cpu->vendor = x86_vendors[i].vendor; 286 break; 287 } 288 } 289 } 290 291 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 292 { 293 c->x86 = (tfms >> 8) & 0xf; 294 c->x86_model = (tfms >> 4) & 0xf; 295 c->x86_mask = tfms & 0xf; 296 if (c->x86 == 0xf) 297 c->x86 += (tfms >> 20) & 0xff; 298 if (c->x86 >= 0x6) 299 c->x86_model += ((tfms >> 16) & 0xF) << 4; 300 } 301 302 int x86_cpu_init_f(void) 303 { 304 const u32 em_rst = ~X86_CR0_EM; 305 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 306 307 /* initialize FPU, reset EM, set MP and NE */ 308 asm ("fninit\n" \ 309 "movl %%cr0, %%eax\n" \ 310 "andl %0, %%eax\n" \ 311 "orl %1, %%eax\n" \ 312 "movl %%eax, %%cr0\n" \ 313 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 314 315 /* identify CPU via cpuid and store the decoded info into gd->arch */ 316 if (has_cpuid()) { 317 struct cpu_device_id cpu; 318 struct cpuinfo_x86 c; 319 320 identify_cpu(&cpu); 321 get_fms(&c, cpu.device); 322 gd->arch.x86 = c.x86; 323 gd->arch.x86_vendor = cpu.vendor; 324 gd->arch.x86_model = c.x86_model; 325 gd->arch.x86_mask = c.x86_mask; 326 gd->arch.x86_device = cpu.device; 327 328 gd->arch.has_mtrr = has_mtrr(); 329 } 330 331 return 0; 332 } 333 334 void x86_enable_caches(void) 335 { 336 unsigned long cr0; 337 338 cr0 = read_cr0(); 339 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 340 write_cr0(cr0); 341 wbinvd(); 342 } 343 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 344 345 void x86_disable_caches(void) 346 { 347 unsigned long cr0; 348 349 cr0 = read_cr0(); 350 cr0 |= X86_CR0_NW | X86_CR0_CD; 351 wbinvd(); 352 write_cr0(cr0); 353 wbinvd(); 354 } 355 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 356 357 int x86_init_cache(void) 358 { 359 enable_caches(); 360 361 return 0; 362 } 363 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 364 365 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 366 { 367 printf("resetting ...\n"); 368 369 /* wait 50 ms */ 370 udelay(50000); 371 disable_interrupts(); 372 reset_cpu(0); 373 374 /*NOTREACHED*/ 375 return 0; 376 } 377 378 void flush_cache(unsigned long dummy1, unsigned long dummy2) 379 { 380 asm("wbinvd\n"); 381 } 382 383 __weak void reset_cpu(ulong addr) 384 { 385 /* Do a hard reset through the chipset's reset control register */ 386 outb(SYS_RST | RST_CPU, PORT_RESET); 387 for (;;) 388 cpu_hlt(); 389 } 390 391 void x86_full_reset(void) 392 { 393 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 394 } 395 396 int dcache_status(void) 397 { 398 return !(read_cr0() & 0x40000000); 399 } 400 401 /* Define these functions to allow ehch-hcd to function */ 402 void flush_dcache_range(unsigned long start, unsigned long stop) 403 { 404 } 405 406 void invalidate_dcache_range(unsigned long start, unsigned long stop) 407 { 408 } 409 410 void dcache_enable(void) 411 { 412 enable_caches(); 413 } 414 415 void dcache_disable(void) 416 { 417 disable_caches(); 418 } 419 420 void icache_enable(void) 421 { 422 } 423 424 void icache_disable(void) 425 { 426 } 427 428 int icache_status(void) 429 { 430 return 1; 431 } 432 433 void cpu_enable_paging_pae(ulong cr3) 434 { 435 __asm__ __volatile__( 436 /* Load the page table address */ 437 "movl %0, %%cr3\n" 438 /* Enable pae */ 439 "movl %%cr4, %%eax\n" 440 "orl $0x00000020, %%eax\n" 441 "movl %%eax, %%cr4\n" 442 /* Enable paging */ 443 "movl %%cr0, %%eax\n" 444 "orl $0x80000000, %%eax\n" 445 "movl %%eax, %%cr0\n" 446 : 447 : "r" (cr3) 448 : "eax"); 449 } 450 451 void cpu_disable_paging_pae(void) 452 { 453 /* Turn off paging */ 454 __asm__ __volatile__ ( 455 /* Disable paging */ 456 "movl %%cr0, %%eax\n" 457 "andl $0x7fffffff, %%eax\n" 458 "movl %%eax, %%cr0\n" 459 /* Disable pae */ 460 "movl %%cr4, %%eax\n" 461 "andl $0xffffffdf, %%eax\n" 462 "movl %%eax, %%cr4\n" 463 : 464 : 465 : "eax"); 466 } 467 468 static bool can_detect_long_mode(void) 469 { 470 return cpuid_eax(0x80000000) > 0x80000000UL; 471 } 472 473 static bool has_long_mode(void) 474 { 475 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 476 } 477 478 int cpu_has_64bit(void) 479 { 480 return has_cpuid() && can_detect_long_mode() && 481 has_long_mode(); 482 } 483 484 const char *cpu_vendor_name(int vendor) 485 { 486 const char *name; 487 name = "<invalid cpu vendor>"; 488 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 489 (x86_vendor_name[vendor] != 0)) 490 name = x86_vendor_name[vendor]; 491 492 return name; 493 } 494 495 char *cpu_get_name(char *name) 496 { 497 unsigned int *name_as_ints = (unsigned int *)name; 498 struct cpuid_result regs; 499 char *ptr; 500 int i; 501 502 /* This bit adds up to 48 bytes */ 503 for (i = 0; i < 3; i++) { 504 regs = cpuid(0x80000002 + i); 505 name_as_ints[i * 4 + 0] = regs.eax; 506 name_as_ints[i * 4 + 1] = regs.ebx; 507 name_as_ints[i * 4 + 2] = regs.ecx; 508 name_as_ints[i * 4 + 3] = regs.edx; 509 } 510 name[CPU_MAX_NAME_LEN - 1] = '\0'; 511 512 /* Skip leading spaces. */ 513 ptr = name; 514 while (*ptr == ' ') 515 ptr++; 516 517 return ptr; 518 } 519 520 int default_print_cpuinfo(void) 521 { 522 printf("CPU: %s, vendor %s, device %xh\n", 523 cpu_has_64bit() ? "x86_64" : "x86", 524 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 525 526 return 0; 527 } 528 529 #define PAGETABLE_SIZE (6 * 4096) 530 531 /** 532 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 533 * 534 * @pgtable: Pointer to a 24iKB block of memory 535 */ 536 static void build_pagetable(uint32_t *pgtable) 537 { 538 uint i; 539 540 memset(pgtable, '\0', PAGETABLE_SIZE); 541 542 /* Level 4 needs a single entry */ 543 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 544 545 /* Level 3 has one 64-bit entry for each GiB of memory */ 546 for (i = 0; i < 4; i++) { 547 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 548 0x1000 * i + 7; 549 } 550 551 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 552 for (i = 0; i < 2048; i++) 553 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 554 } 555 556 int cpu_jump_to_64bit(ulong setup_base, ulong target) 557 { 558 uint32_t *pgtable; 559 560 pgtable = memalign(4096, PAGETABLE_SIZE); 561 if (!pgtable) 562 return -ENOMEM; 563 564 build_pagetable(pgtable); 565 cpu_call64((ulong)pgtable, setup_base, target); 566 free(pgtable); 567 568 return -EFAULT; 569 } 570 571 void show_boot_progress(int val) 572 { 573 #if MIN_PORT80_KCLOCKS_DELAY 574 /* 575 * Scale the time counter reading to avoid using 64 bit arithmetics. 576 * Can't use get_timer() here becuase it could be not yet 577 * initialized or even implemented. 578 */ 579 if (!gd->arch.tsc_prev) { 580 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 581 gd->arch.tsc_prev = 0; 582 } else { 583 uint32_t now; 584 585 do { 586 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 587 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 588 gd->arch.tsc_prev = now; 589 } 590 #endif 591 outb(val, POST_PORT); 592 } 593 594 #ifndef CONFIG_SYS_COREBOOT 595 int last_stage_init(void) 596 { 597 write_tables(); 598 599 return 0; 600 } 601 #endif 602