1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <errno.h> 25 #include <malloc.h> 26 #include <asm/control_regs.h> 27 #include <asm/cpu.h> 28 #include <asm/processor.h> 29 #include <asm/processor-flags.h> 30 #include <asm/interrupt.h> 31 #include <linux/compiler.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* 36 * Constructor for a conventional segment GDT (or LDT) entry 37 * This is a macro so it can be used in initialisers 38 */ 39 #define GDT_ENTRY(flags, base, limit) \ 40 ((((base) & 0xff000000ULL) << (56-24)) | \ 41 (((flags) & 0x0000f0ffULL) << 40) | \ 42 (((limit) & 0x000f0000ULL) << (48-16)) | \ 43 (((base) & 0x00ffffffULL) << 16) | \ 44 (((limit) & 0x0000ffffULL))) 45 46 struct gdt_ptr { 47 u16 len; 48 u32 ptr; 49 } __packed; 50 51 struct cpu_device_id { 52 unsigned vendor; 53 unsigned device; 54 }; 55 56 struct cpuinfo_x86 { 57 uint8_t x86; /* CPU family */ 58 uint8_t x86_vendor; /* CPU vendor */ 59 uint8_t x86_model; 60 uint8_t x86_mask; 61 }; 62 63 /* 64 * List of cpu vendor strings along with their normalized 65 * id values. 66 */ 67 static struct { 68 int vendor; 69 const char *name; 70 } x86_vendors[] = { 71 { X86_VENDOR_INTEL, "GenuineIntel", }, 72 { X86_VENDOR_CYRIX, "CyrixInstead", }, 73 { X86_VENDOR_AMD, "AuthenticAMD", }, 74 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 75 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 76 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 77 { X86_VENDOR_RISE, "RiseRiseRise", }, 78 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 79 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 80 { X86_VENDOR_NSC, "Geode by NSC", }, 81 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 82 }; 83 84 static const char *const x86_vendor_name[] = { 85 [X86_VENDOR_INTEL] = "Intel", 86 [X86_VENDOR_CYRIX] = "Cyrix", 87 [X86_VENDOR_AMD] = "AMD", 88 [X86_VENDOR_UMC] = "UMC", 89 [X86_VENDOR_NEXGEN] = "NexGen", 90 [X86_VENDOR_CENTAUR] = "Centaur", 91 [X86_VENDOR_RISE] = "Rise", 92 [X86_VENDOR_TRANSMETA] = "Transmeta", 93 [X86_VENDOR_NSC] = "NSC", 94 [X86_VENDOR_SIS] = "SiS", 95 }; 96 97 static void load_ds(u32 segment) 98 { 99 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 100 } 101 102 static void load_es(u32 segment) 103 { 104 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 105 } 106 107 static void load_fs(u32 segment) 108 { 109 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 110 } 111 112 static void load_gs(u32 segment) 113 { 114 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 115 } 116 117 static void load_ss(u32 segment) 118 { 119 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 120 } 121 122 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 123 { 124 struct gdt_ptr gdt; 125 126 gdt.len = (num_entries * 8) - 1; 127 gdt.ptr = (u32)boot_gdt; 128 129 asm volatile("lgdtl %0\n" : : "m" (gdt)); 130 } 131 132 void setup_gdt(gd_t *id, u64 *gdt_addr) 133 { 134 /* CS: code, read/execute, 4 GB, base 0 */ 135 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 136 137 /* DS: data, read/write, 4 GB, base 0 */ 138 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 139 140 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 141 id->arch.gd_addr = id; 142 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 143 (ulong)&id->arch.gd_addr, 0xfffff); 144 145 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 146 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); 147 148 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 149 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); 150 151 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 152 load_ds(X86_GDT_ENTRY_32BIT_DS); 153 load_es(X86_GDT_ENTRY_32BIT_DS); 154 load_gs(X86_GDT_ENTRY_32BIT_DS); 155 load_ss(X86_GDT_ENTRY_32BIT_DS); 156 load_fs(X86_GDT_ENTRY_32BIT_FS); 157 } 158 159 int __weak x86_cleanup_before_linux(void) 160 { 161 #ifdef CONFIG_BOOTSTAGE_STASH 162 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, 163 CONFIG_BOOTSTAGE_STASH_SIZE); 164 #endif 165 166 return 0; 167 } 168 169 /* 170 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 171 * by the fact that they preserve the flags across the division of 5/2. 172 * PII and PPro exhibit this behavior too, but they have cpuid available. 173 */ 174 175 /* 176 * Perform the Cyrix 5/2 test. A Cyrix won't change 177 * the flags, while other 486 chips will. 178 */ 179 static inline int test_cyrix_52div(void) 180 { 181 unsigned int test; 182 183 __asm__ __volatile__( 184 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 185 "div %b2\n\t" /* divide 5 by 2 */ 186 "lahf" /* store flags into %ah */ 187 : "=a" (test) 188 : "0" (5), "q" (2) 189 : "cc"); 190 191 /* AH is 0x02 on Cyrix after the divide.. */ 192 return (unsigned char) (test >> 8) == 0x02; 193 } 194 195 /* 196 * Detect a NexGen CPU running without BIOS hypercode new enough 197 * to have CPUID. (Thanks to Herbert Oppmann) 198 */ 199 200 static int deep_magic_nexgen_probe(void) 201 { 202 int ret; 203 204 __asm__ __volatile__ ( 205 " movw $0x5555, %%ax\n" 206 " xorw %%dx,%%dx\n" 207 " movw $2, %%cx\n" 208 " divw %%cx\n" 209 " movl $0, %%eax\n" 210 " jnz 1f\n" 211 " movl $1, %%eax\n" 212 "1:\n" 213 : "=a" (ret) : : "cx", "dx"); 214 return ret; 215 } 216 217 static bool has_cpuid(void) 218 { 219 return flag_is_changeable_p(X86_EFLAGS_ID); 220 } 221 222 static int build_vendor_name(char *vendor_name) 223 { 224 struct cpuid_result result; 225 result = cpuid(0x00000000); 226 unsigned int *name_as_ints = (unsigned int *)vendor_name; 227 228 name_as_ints[0] = result.ebx; 229 name_as_ints[1] = result.edx; 230 name_as_ints[2] = result.ecx; 231 232 return result.eax; 233 } 234 235 static void identify_cpu(struct cpu_device_id *cpu) 236 { 237 char vendor_name[16]; 238 int i; 239 240 vendor_name[0] = '\0'; /* Unset */ 241 242 /* Find the id and vendor_name */ 243 if (!has_cpuid()) { 244 /* Its a 486 if we can modify the AC flag */ 245 if (flag_is_changeable_p(X86_EFLAGS_AC)) 246 cpu->device = 0x00000400; /* 486 */ 247 else 248 cpu->device = 0x00000300; /* 386 */ 249 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 250 memcpy(vendor_name, "CyrixInstead", 13); 251 /* If we ever care we can enable cpuid here */ 252 } 253 /* Detect NexGen with old hypercode */ 254 else if (deep_magic_nexgen_probe()) 255 memcpy(vendor_name, "NexGenDriven", 13); 256 } 257 if (has_cpuid()) { 258 int cpuid_level; 259 260 cpuid_level = build_vendor_name(vendor_name); 261 vendor_name[12] = '\0'; 262 263 /* Intel-defined flags: level 0x00000001 */ 264 if (cpuid_level >= 0x00000001) { 265 cpu->device = cpuid_eax(0x00000001); 266 } else { 267 /* Have CPUID level 0 only unheard of */ 268 cpu->device = 0x00000400; 269 } 270 } 271 cpu->vendor = X86_VENDOR_UNKNOWN; 272 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 273 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 274 cpu->vendor = x86_vendors[i].vendor; 275 break; 276 } 277 } 278 } 279 280 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 281 { 282 c->x86 = (tfms >> 8) & 0xf; 283 c->x86_model = (tfms >> 4) & 0xf; 284 c->x86_mask = tfms & 0xf; 285 if (c->x86 == 0xf) 286 c->x86 += (tfms >> 20) & 0xff; 287 if (c->x86 >= 0x6) 288 c->x86_model += ((tfms >> 16) & 0xF) << 4; 289 } 290 291 int x86_cpu_init_f(void) 292 { 293 const u32 em_rst = ~X86_CR0_EM; 294 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 295 296 /* initialize FPU, reset EM, set MP and NE */ 297 asm ("fninit\n" \ 298 "movl %%cr0, %%eax\n" \ 299 "andl %0, %%eax\n" \ 300 "orl %1, %%eax\n" \ 301 "movl %%eax, %%cr0\n" \ 302 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 303 304 /* identify CPU via cpuid and store the decoded info into gd->arch */ 305 if (has_cpuid()) { 306 struct cpu_device_id cpu; 307 struct cpuinfo_x86 c; 308 309 identify_cpu(&cpu); 310 get_fms(&c, cpu.device); 311 gd->arch.x86 = c.x86; 312 gd->arch.x86_vendor = cpu.vendor; 313 gd->arch.x86_model = c.x86_model; 314 gd->arch.x86_mask = c.x86_mask; 315 gd->arch.x86_device = cpu.device; 316 } 317 318 return 0; 319 } 320 321 int x86_cpu_init_r(void) 322 { 323 /* Initialize core interrupt and exception functionality of CPU */ 324 cpu_init_interrupts(); 325 return 0; 326 } 327 int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); 328 329 void x86_enable_caches(void) 330 { 331 unsigned long cr0; 332 333 cr0 = read_cr0(); 334 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 335 write_cr0(cr0); 336 wbinvd(); 337 } 338 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 339 340 void x86_disable_caches(void) 341 { 342 unsigned long cr0; 343 344 cr0 = read_cr0(); 345 cr0 |= X86_CR0_NW | X86_CR0_CD; 346 wbinvd(); 347 write_cr0(cr0); 348 wbinvd(); 349 } 350 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 351 352 int x86_init_cache(void) 353 { 354 enable_caches(); 355 356 return 0; 357 } 358 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 359 360 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 361 { 362 printf("resetting ...\n"); 363 364 /* wait 50 ms */ 365 udelay(50000); 366 disable_interrupts(); 367 reset_cpu(0); 368 369 /*NOTREACHED*/ 370 return 0; 371 } 372 373 void flush_cache(unsigned long dummy1, unsigned long dummy2) 374 { 375 asm("wbinvd\n"); 376 } 377 378 void __attribute__ ((regparm(0))) generate_gpf(void); 379 380 /* segment 0x70 is an arbitrary segment which does not exist */ 381 asm(".globl generate_gpf\n" 382 ".hidden generate_gpf\n" 383 ".type generate_gpf, @function\n" 384 "generate_gpf:\n" 385 "ljmp $0x70, $0x47114711\n"); 386 387 __weak void reset_cpu(ulong addr) 388 { 389 printf("Resetting using x86 Triple Fault\n"); 390 set_vector(13, generate_gpf); /* general protection fault handler */ 391 set_vector(8, generate_gpf); /* double fault handler */ 392 generate_gpf(); /* start the show */ 393 } 394 395 int dcache_status(void) 396 { 397 return !(read_cr0() & 0x40000000); 398 } 399 400 /* Define these functions to allow ehch-hcd to function */ 401 void flush_dcache_range(unsigned long start, unsigned long stop) 402 { 403 } 404 405 void invalidate_dcache_range(unsigned long start, unsigned long stop) 406 { 407 } 408 409 void dcache_enable(void) 410 { 411 enable_caches(); 412 } 413 414 void dcache_disable(void) 415 { 416 disable_caches(); 417 } 418 419 void icache_enable(void) 420 { 421 } 422 423 void icache_disable(void) 424 { 425 } 426 427 int icache_status(void) 428 { 429 return 1; 430 } 431 432 void cpu_enable_paging_pae(ulong cr3) 433 { 434 __asm__ __volatile__( 435 /* Load the page table address */ 436 "movl %0, %%cr3\n" 437 /* Enable pae */ 438 "movl %%cr4, %%eax\n" 439 "orl $0x00000020, %%eax\n" 440 "movl %%eax, %%cr4\n" 441 /* Enable paging */ 442 "movl %%cr0, %%eax\n" 443 "orl $0x80000000, %%eax\n" 444 "movl %%eax, %%cr0\n" 445 : 446 : "r" (cr3) 447 : "eax"); 448 } 449 450 void cpu_disable_paging_pae(void) 451 { 452 /* Turn off paging */ 453 __asm__ __volatile__ ( 454 /* Disable paging */ 455 "movl %%cr0, %%eax\n" 456 "andl $0x7fffffff, %%eax\n" 457 "movl %%eax, %%cr0\n" 458 /* Disable pae */ 459 "movl %%cr4, %%eax\n" 460 "andl $0xffffffdf, %%eax\n" 461 "movl %%eax, %%cr4\n" 462 : 463 : 464 : "eax"); 465 } 466 467 static bool can_detect_long_mode(void) 468 { 469 return cpuid_eax(0x80000000) > 0x80000000UL; 470 } 471 472 static bool has_long_mode(void) 473 { 474 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 475 } 476 477 int cpu_has_64bit(void) 478 { 479 return has_cpuid() && can_detect_long_mode() && 480 has_long_mode(); 481 } 482 483 const char *cpu_vendor_name(int vendor) 484 { 485 const char *name; 486 name = "<invalid cpu vendor>"; 487 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 488 (x86_vendor_name[vendor] != 0)) 489 name = x86_vendor_name[vendor]; 490 491 return name; 492 } 493 494 void fill_processor_name(char *processor_name) 495 { 496 struct cpuid_result regs; 497 char temp_processor_name[49]; 498 char *processor_name_start; 499 unsigned int *name_as_ints = (unsigned int *)temp_processor_name; 500 int i; 501 502 for (i = 0; i < 3; i++) { 503 regs = cpuid(0x80000002 + i); 504 name_as_ints[i * 4 + 0] = regs.eax; 505 name_as_ints[i * 4 + 1] = regs.ebx; 506 name_as_ints[i * 4 + 2] = regs.ecx; 507 name_as_ints[i * 4 + 3] = regs.edx; 508 } 509 510 temp_processor_name[48] = 0; 511 512 /* Skip leading spaces. */ 513 processor_name_start = temp_processor_name; 514 while (*processor_name_start == ' ') 515 processor_name_start++; 516 517 memset(processor_name, 0, 49); 518 strcpy(processor_name, processor_name_start); 519 } 520 521 int print_cpuinfo(void) 522 { 523 printf("CPU: %s, vendor %s, device %xh\n", 524 cpu_has_64bit() ? "x86_64" : "x86", 525 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 526 527 return 0; 528 } 529 530 #define PAGETABLE_SIZE (6 * 4096) 531 532 /** 533 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 534 * 535 * @pgtable: Pointer to a 24iKB block of memory 536 */ 537 static void build_pagetable(uint32_t *pgtable) 538 { 539 uint i; 540 541 memset(pgtable, '\0', PAGETABLE_SIZE); 542 543 /* Level 4 needs a single entry */ 544 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 545 546 /* Level 3 has one 64-bit entry for each GiB of memory */ 547 for (i = 0; i < 4; i++) { 548 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 549 0x1000 * i + 7; 550 } 551 552 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 553 for (i = 0; i < 2048; i++) 554 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 555 } 556 557 int cpu_jump_to_64bit(ulong setup_base, ulong target) 558 { 559 uint32_t *pgtable; 560 561 pgtable = memalign(4096, PAGETABLE_SIZE); 562 if (!pgtable) 563 return -ENOMEM; 564 565 build_pagetable(pgtable); 566 cpu_call64((ulong)pgtable, setup_base, target); 567 free(pgtable); 568 569 return -EFAULT; 570 } 571