xref: /rk3399_rockchip-uboot/arch/x86/cpu/cpu.c (revision f30fc4de4160300b90859958a4785c065483e69f)
1fea25720SGraeme Russ /*
2fea25720SGraeme Russ  * (C) Copyright 2008-2011
3fea25720SGraeme Russ  * Graeme Russ, <graeme.russ@gmail.com>
4fea25720SGraeme Russ  *
5fea25720SGraeme Russ  * (C) Copyright 2002
6fa82f871SAlbert ARIBAUD  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7fea25720SGraeme Russ  *
8fea25720SGraeme Russ  * (C) Copyright 2002
9fea25720SGraeme Russ  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10fea25720SGraeme Russ  * Marius Groeger <mgroeger@sysgo.de>
11fea25720SGraeme Russ  *
12fea25720SGraeme Russ  * (C) Copyright 2002
13fea25720SGraeme Russ  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14fea25720SGraeme Russ  * Alex Zuepke <azu@sysgo.de>
15fea25720SGraeme Russ  *
16fea25720SGraeme Russ  * See file CREDITS for list of people who contributed to this
17fea25720SGraeme Russ  * project.
18fea25720SGraeme Russ  *
19fea25720SGraeme Russ  * This program is free software; you can redistribute it and/or
20fea25720SGraeme Russ  * modify it under the terms of the GNU General Public License as
21fea25720SGraeme Russ  * published by the Free Software Foundation; either version 2 of
22fea25720SGraeme Russ  * the License, or (at your option) any later version.
23fea25720SGraeme Russ  *
24fea25720SGraeme Russ  * This program is distributed in the hope that it will be useful,
25fea25720SGraeme Russ  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26fea25720SGraeme Russ  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27fea25720SGraeme Russ  * GNU General Public License for more details.
28fea25720SGraeme Russ  *
29fea25720SGraeme Russ  * You should have received a copy of the GNU General Public License
30fea25720SGraeme Russ  * along with this program; if not, write to the Free Software
31fea25720SGraeme Russ  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32fea25720SGraeme Russ  * MA 02111-1307 USA
33fea25720SGraeme Russ  */
34fea25720SGraeme Russ 
35fea25720SGraeme Russ #include <common.h>
36fea25720SGraeme Russ #include <command.h>
37fea25720SGraeme Russ #include <asm/processor.h>
38fea25720SGraeme Russ #include <asm/processor-flags.h>
39fea25720SGraeme Russ #include <asm/interrupt.h>
4060a9b6bfSGabe Black #include <linux/compiler.h>
41fea25720SGraeme Russ 
42fea25720SGraeme Russ /*
43fea25720SGraeme Russ  * Constructor for a conventional segment GDT (or LDT) entry
44fea25720SGraeme Russ  * This is a macro so it can be used in initialisers
45fea25720SGraeme Russ  */
46fea25720SGraeme Russ #define GDT_ENTRY(flags, base, limit)			\
47fea25720SGraeme Russ 	((((base)  & 0xff000000ULL) << (56-24)) |	\
48fea25720SGraeme Russ 	 (((flags) & 0x0000f0ffULL) << 40) |		\
49fea25720SGraeme Russ 	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
50fea25720SGraeme Russ 	 (((base)  & 0x00ffffffULL) << 16) |		\
51fea25720SGraeme Russ 	 (((limit) & 0x0000ffffULL)))
52fea25720SGraeme Russ 
53fea25720SGraeme Russ struct gdt_ptr {
54fea25720SGraeme Russ 	u16 len;
55fea25720SGraeme Russ 	u32 ptr;
56717979fdSGraeme Russ } __packed;
57fea25720SGraeme Russ 
5874bfbe1bSGraeme Russ static void load_ds(u32 segment)
59fea25720SGraeme Russ {
6074bfbe1bSGraeme Russ 	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
6174bfbe1bSGraeme Russ }
62fea25720SGraeme Russ 
6374bfbe1bSGraeme Russ static void load_es(u32 segment)
6474bfbe1bSGraeme Russ {
6574bfbe1bSGraeme Russ 	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
6674bfbe1bSGraeme Russ }
67fea25720SGraeme Russ 
6874bfbe1bSGraeme Russ static void load_fs(u32 segment)
6974bfbe1bSGraeme Russ {
7074bfbe1bSGraeme Russ 	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
7174bfbe1bSGraeme Russ }
7274bfbe1bSGraeme Russ 
7374bfbe1bSGraeme Russ static void load_gs(u32 segment)
7474bfbe1bSGraeme Russ {
7574bfbe1bSGraeme Russ 	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
7674bfbe1bSGraeme Russ }
7774bfbe1bSGraeme Russ 
7874bfbe1bSGraeme Russ static void load_ss(u32 segment)
7974bfbe1bSGraeme Russ {
8074bfbe1bSGraeme Russ 	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
8174bfbe1bSGraeme Russ }
8274bfbe1bSGraeme Russ 
8374bfbe1bSGraeme Russ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
8474bfbe1bSGraeme Russ {
8574bfbe1bSGraeme Russ 	struct gdt_ptr gdt;
8674bfbe1bSGraeme Russ 
8774bfbe1bSGraeme Russ 	gdt.len = (num_entries * 8) - 1;
8874bfbe1bSGraeme Russ 	gdt.ptr = (u32)boot_gdt;
8974bfbe1bSGraeme Russ 
9074bfbe1bSGraeme Russ 	asm volatile("lgdtl %0\n" : : "m" (gdt));
91fea25720SGraeme Russ }
92fea25720SGraeme Russ 
939e6c572fSGraeme Russ void setup_gdt(gd_t *id, u64 *gdt_addr)
949e6c572fSGraeme Russ {
959e6c572fSGraeme Russ 	/* CS: code, read/execute, 4 GB, base 0 */
969e6c572fSGraeme Russ 	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
979e6c572fSGraeme Russ 
989e6c572fSGraeme Russ 	/* DS: data, read/write, 4 GB, base 0 */
999e6c572fSGraeme Russ 	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
1009e6c572fSGraeme Russ 
1019e6c572fSGraeme Russ 	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
1029e6c572fSGraeme Russ 	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, (ulong)id, 0xfffff);
1039e6c572fSGraeme Russ 
1049e6c572fSGraeme Russ 	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
1059e6c572fSGraeme Russ 	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
1069e6c572fSGraeme Russ 
1079e6c572fSGraeme Russ 	/* 16-bit DS: data, read/write, 64 kB, base 0 */
1089e6c572fSGraeme Russ 	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
1099e6c572fSGraeme Russ 
1109e6c572fSGraeme Russ 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
1119e6c572fSGraeme Russ 	load_ds(X86_GDT_ENTRY_32BIT_DS);
1129e6c572fSGraeme Russ 	load_es(X86_GDT_ENTRY_32BIT_DS);
1139e6c572fSGraeme Russ 	load_gs(X86_GDT_ENTRY_32BIT_DS);
1149e6c572fSGraeme Russ 	load_ss(X86_GDT_ENTRY_32BIT_DS);
1159e6c572fSGraeme Russ 	load_fs(X86_GDT_ENTRY_32BIT_FS);
1169e6c572fSGraeme Russ }
1179e6c572fSGraeme Russ 
118*f30fc4deSGabe Black int __weak x86_cleanup_before_linux(void)
119*f30fc4deSGabe Black {
120*f30fc4deSGabe Black 	return 0;
121*f30fc4deSGabe Black }
122*f30fc4deSGabe Black 
123fea25720SGraeme Russ int x86_cpu_init_f(void)
124fea25720SGraeme Russ {
125fea25720SGraeme Russ 	const u32 em_rst = ~X86_CR0_EM;
126fea25720SGraeme Russ 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
127fea25720SGraeme Russ 
128fea25720SGraeme Russ 	/* initialize FPU, reset EM, set MP and NE */
129fea25720SGraeme Russ 	asm ("fninit\n" \
130fea25720SGraeme Russ 	     "movl %%cr0, %%eax\n" \
131fea25720SGraeme Russ 	     "andl %0, %%eax\n" \
132fea25720SGraeme Russ 	     "orl  %1, %%eax\n" \
133fea25720SGraeme Russ 	     "movl %%eax, %%cr0\n" \
134fea25720SGraeme Russ 	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
135fea25720SGraeme Russ 
136fea25720SGraeme Russ 	return 0;
137fea25720SGraeme Russ }
138fea25720SGraeme Russ int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
139fea25720SGraeme Russ 
140fea25720SGraeme Russ int x86_cpu_init_r(void)
141fea25720SGraeme Russ {
142d653244bSGraeme Russ 	/* Initialize core interrupt and exception functionality of CPU */
143d653244bSGraeme Russ 	cpu_init_interrupts();
144d653244bSGraeme Russ 	return 0;
145d653244bSGraeme Russ }
146d653244bSGraeme Russ int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
147d653244bSGraeme Russ 
148d653244bSGraeme Russ void x86_enable_caches(void)
149d653244bSGraeme Russ {
150fea25720SGraeme Russ 	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
151fea25720SGraeme Russ 
152fea25720SGraeme Russ 	/* turn on the cache and disable write through */
153fea25720SGraeme Russ 	asm("movl	%%cr0, %%eax\n"
154fea25720SGraeme Russ 	    "andl	%0, %%eax\n"
155fea25720SGraeme Russ 	    "movl	%%eax, %%cr0\n"
156fea25720SGraeme Russ 	    "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
157d653244bSGraeme Russ }
158d653244bSGraeme Russ void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
159fea25720SGraeme Russ 
160d653244bSGraeme Russ int x86_init_cache(void)
161d653244bSGraeme Russ {
162d653244bSGraeme Russ 	enable_caches();
163d653244bSGraeme Russ 
164fea25720SGraeme Russ 	return 0;
165fea25720SGraeme Russ }
166d653244bSGraeme Russ int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
167fea25720SGraeme Russ 
168fea25720SGraeme Russ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
169fea25720SGraeme Russ {
170fea25720SGraeme Russ 	printf("resetting ...\n");
171fea25720SGraeme Russ 
172fea25720SGraeme Russ 	/* wait 50 ms */
173fea25720SGraeme Russ 	udelay(50000);
174fea25720SGraeme Russ 	disable_interrupts();
175fea25720SGraeme Russ 	reset_cpu(0);
176fea25720SGraeme Russ 
177fea25720SGraeme Russ 	/*NOTREACHED*/
178fea25720SGraeme Russ 	return 0;
179fea25720SGraeme Russ }
180fea25720SGraeme Russ 
181fea25720SGraeme Russ void  flush_cache(unsigned long dummy1, unsigned long dummy2)
182fea25720SGraeme Russ {
183fea25720SGraeme Russ 	asm("wbinvd\n");
184fea25720SGraeme Russ }
185fea25720SGraeme Russ 
186fea25720SGraeme Russ void __attribute__ ((regparm(0))) generate_gpf(void);
187fea25720SGraeme Russ 
188fea25720SGraeme Russ /* segment 0x70 is an arbitrary segment which does not exist */
189fea25720SGraeme Russ asm(".globl generate_gpf\n"
190fea25720SGraeme Russ 	".hidden generate_gpf\n"
191fea25720SGraeme Russ 	".type generate_gpf, @function\n"
192fea25720SGraeme Russ 	"generate_gpf:\n"
193fea25720SGraeme Russ 	"ljmp   $0x70, $0x47114711\n");
194fea25720SGraeme Russ 
195fea25720SGraeme Russ void __reset_cpu(ulong addr)
196fea25720SGraeme Russ {
197fea25720SGraeme Russ 	printf("Resetting using x86 Triple Fault\n");
198fea25720SGraeme Russ 	set_vector(13, generate_gpf);	/* general protection fault handler */
199fea25720SGraeme Russ 	set_vector(8, generate_gpf);	/* double fault handler */
200fea25720SGraeme Russ 	generate_gpf();			/* start the show */
201fea25720SGraeme Russ }
202fea25720SGraeme Russ void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
203