xref: /rk3399_rockchip-uboot/arch/x86/cpu/cpu.c (revision 74bfbe1ba5ba99adccdc26dc4adbfb9221849310)
1fea25720SGraeme Russ /*
2fea25720SGraeme Russ  * (C) Copyright 2008-2011
3fea25720SGraeme Russ  * Graeme Russ, <graeme.russ@gmail.com>
4fea25720SGraeme Russ  *
5fea25720SGraeme Russ  * (C) Copyright 2002
6fa82f871SAlbert ARIBAUD  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7fea25720SGraeme Russ  *
8fea25720SGraeme Russ  * (C) Copyright 2002
9fea25720SGraeme Russ  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10fea25720SGraeme Russ  * Marius Groeger <mgroeger@sysgo.de>
11fea25720SGraeme Russ  *
12fea25720SGraeme Russ  * (C) Copyright 2002
13fea25720SGraeme Russ  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14fea25720SGraeme Russ  * Alex Zuepke <azu@sysgo.de>
15fea25720SGraeme Russ  *
16fea25720SGraeme Russ  * See file CREDITS for list of people who contributed to this
17fea25720SGraeme Russ  * project.
18fea25720SGraeme Russ  *
19fea25720SGraeme Russ  * This program is free software; you can redistribute it and/or
20fea25720SGraeme Russ  * modify it under the terms of the GNU General Public License as
21fea25720SGraeme Russ  * published by the Free Software Foundation; either version 2 of
22fea25720SGraeme Russ  * the License, or (at your option) any later version.
23fea25720SGraeme Russ  *
24fea25720SGraeme Russ  * This program is distributed in the hope that it will be useful,
25fea25720SGraeme Russ  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26fea25720SGraeme Russ  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27fea25720SGraeme Russ  * GNU General Public License for more details.
28fea25720SGraeme Russ  *
29fea25720SGraeme Russ  * You should have received a copy of the GNU General Public License
30fea25720SGraeme Russ  * along with this program; if not, write to the Free Software
31fea25720SGraeme Russ  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32fea25720SGraeme Russ  * MA 02111-1307 USA
33fea25720SGraeme Russ  */
34fea25720SGraeme Russ 
35fea25720SGraeme Russ #include <common.h>
36fea25720SGraeme Russ #include <command.h>
37fea25720SGraeme Russ #include <asm/processor.h>
38fea25720SGraeme Russ #include <asm/processor-flags.h>
39fea25720SGraeme Russ #include <asm/interrupt.h>
4060a9b6bfSGabe Black #include <linux/compiler.h>
41fea25720SGraeme Russ 
42fea25720SGraeme Russ /*
43fea25720SGraeme Russ  * Constructor for a conventional segment GDT (or LDT) entry
44fea25720SGraeme Russ  * This is a macro so it can be used in initialisers
45fea25720SGraeme Russ  */
46fea25720SGraeme Russ #define GDT_ENTRY(flags, base, limit)			\
47fea25720SGraeme Russ 	((((base)  & 0xff000000ULL) << (56-24)) |	\
48fea25720SGraeme Russ 	 (((flags) & 0x0000f0ffULL) << 40) |		\
49fea25720SGraeme Russ 	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
50fea25720SGraeme Russ 	 (((base)  & 0x00ffffffULL) << 16) |		\
51fea25720SGraeme Russ 	 (((limit) & 0x0000ffffULL)))
52fea25720SGraeme Russ 
53fea25720SGraeme Russ struct gdt_ptr {
54fea25720SGraeme Russ 	u16 len;
55fea25720SGraeme Russ 	u32 ptr;
56717979fdSGraeme Russ } __packed;
57fea25720SGraeme Russ 
58*74bfbe1bSGraeme Russ static void load_ds(u32 segment)
59fea25720SGraeme Russ {
60*74bfbe1bSGraeme Russ 	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
61*74bfbe1bSGraeme Russ }
62fea25720SGraeme Russ 
63*74bfbe1bSGraeme Russ static void load_es(u32 segment)
64*74bfbe1bSGraeme Russ {
65*74bfbe1bSGraeme Russ 	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
66*74bfbe1bSGraeme Russ }
67fea25720SGraeme Russ 
68*74bfbe1bSGraeme Russ static void load_fs(u32 segment)
69*74bfbe1bSGraeme Russ {
70*74bfbe1bSGraeme Russ 	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
71*74bfbe1bSGraeme Russ }
72*74bfbe1bSGraeme Russ 
73*74bfbe1bSGraeme Russ static void load_gs(u32 segment)
74*74bfbe1bSGraeme Russ {
75*74bfbe1bSGraeme Russ 	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
76*74bfbe1bSGraeme Russ }
77*74bfbe1bSGraeme Russ 
78*74bfbe1bSGraeme Russ static void load_ss(u32 segment)
79*74bfbe1bSGraeme Russ {
80*74bfbe1bSGraeme Russ 	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
81*74bfbe1bSGraeme Russ }
82*74bfbe1bSGraeme Russ 
83*74bfbe1bSGraeme Russ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
84*74bfbe1bSGraeme Russ {
85*74bfbe1bSGraeme Russ 	struct gdt_ptr gdt;
86*74bfbe1bSGraeme Russ 
87*74bfbe1bSGraeme Russ 	gdt.len = (num_entries * 8) - 1;
88*74bfbe1bSGraeme Russ 	gdt.ptr = (u32)boot_gdt;
89*74bfbe1bSGraeme Russ 
90*74bfbe1bSGraeme Russ 	asm volatile("lgdtl %0\n" : : "m" (gdt));
91fea25720SGraeme Russ }
92fea25720SGraeme Russ 
93fea25720SGraeme Russ int x86_cpu_init_f(void)
94fea25720SGraeme Russ {
95fea25720SGraeme Russ 	const u32 em_rst = ~X86_CR0_EM;
96fea25720SGraeme Russ 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
97fea25720SGraeme Russ 
98fea25720SGraeme Russ 	/* initialize FPU, reset EM, set MP and NE */
99fea25720SGraeme Russ 	asm ("fninit\n" \
100fea25720SGraeme Russ 	     "movl %%cr0, %%eax\n" \
101fea25720SGraeme Russ 	     "andl %0, %%eax\n" \
102fea25720SGraeme Russ 	     "orl  %1, %%eax\n" \
103fea25720SGraeme Russ 	     "movl %%eax, %%cr0\n" \
104fea25720SGraeme Russ 	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
105fea25720SGraeme Russ 
106fea25720SGraeme Russ 	return 0;
107fea25720SGraeme Russ }
108fea25720SGraeme Russ int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
109fea25720SGraeme Russ 
110fea25720SGraeme Russ int x86_cpu_init_r(void)
111fea25720SGraeme Russ {
112fea25720SGraeme Russ 	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
113fea25720SGraeme Russ 
114fea25720SGraeme Russ 	/* turn on the cache and disable write through */
115fea25720SGraeme Russ 	asm("movl	%%cr0, %%eax\n"
116fea25720SGraeme Russ 	    "andl	%0, %%eax\n"
117fea25720SGraeme Russ 	    "movl	%%eax, %%cr0\n"
118fea25720SGraeme Russ 	    "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
119fea25720SGraeme Russ 
120*74bfbe1bSGraeme Russ 	/*
121*74bfbe1bSGraeme Russ 	 * There are machines which are known to not boot with the GDT
122*74bfbe1bSGraeme Russ 	 * being 8-byte unaligned. Intel recommends 16 byte alignment
123*74bfbe1bSGraeme Russ 	 */
124*74bfbe1bSGraeme Russ 	static const u64 boot_gdt[] __aligned(16) = {
125*74bfbe1bSGraeme Russ 		/* CS: code, read/execute, 4 GB, base 0 */
126*74bfbe1bSGraeme Russ 		[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
127*74bfbe1bSGraeme Russ 		/* DS: data, read/write, 4 GB, base 0 */
128*74bfbe1bSGraeme Russ 		[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
129*74bfbe1bSGraeme Russ 		/* 16-bit CS: code, read/execute, 64 kB, base 0 */
130*74bfbe1bSGraeme Russ 		[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff),
131*74bfbe1bSGraeme Russ 		/* 16-bit DS: data, read/write, 64 kB, base 0 */
132*74bfbe1bSGraeme Russ 		[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff),
133*74bfbe1bSGraeme Russ 	};
134*74bfbe1bSGraeme Russ 
135*74bfbe1bSGraeme Russ 	load_gdt(boot_gdt, X86_GDT_NUM_ENTRIES);
136*74bfbe1bSGraeme Russ 	load_ds(X86_GDT_ENTRY_32BIT_DS);
137*74bfbe1bSGraeme Russ 	load_es(X86_GDT_ENTRY_32BIT_DS);
138*74bfbe1bSGraeme Russ 	load_fs(X86_GDT_ENTRY_32BIT_DS);
139*74bfbe1bSGraeme Russ 	load_gs(X86_GDT_ENTRY_32BIT_DS);
140*74bfbe1bSGraeme Russ 	load_ss(X86_GDT_ENTRY_32BIT_DS);
141fea25720SGraeme Russ 
142fea25720SGraeme Russ 	/* Initialize core interrupt and exception functionality of CPU */
143fea25720SGraeme Russ 	cpu_init_interrupts();
144fea25720SGraeme Russ 	return 0;
145fea25720SGraeme Russ }
146fea25720SGraeme Russ int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
147fea25720SGraeme Russ 
148fea25720SGraeme Russ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
149fea25720SGraeme Russ {
150fea25720SGraeme Russ 	printf("resetting ...\n");
151fea25720SGraeme Russ 
152fea25720SGraeme Russ 	/* wait 50 ms */
153fea25720SGraeme Russ 	udelay(50000);
154fea25720SGraeme Russ 	disable_interrupts();
155fea25720SGraeme Russ 	reset_cpu(0);
156fea25720SGraeme Russ 
157fea25720SGraeme Russ 	/*NOTREACHED*/
158fea25720SGraeme Russ 	return 0;
159fea25720SGraeme Russ }
160fea25720SGraeme Russ 
161fea25720SGraeme Russ void  flush_cache(unsigned long dummy1, unsigned long dummy2)
162fea25720SGraeme Russ {
163fea25720SGraeme Russ 	asm("wbinvd\n");
164fea25720SGraeme Russ }
165fea25720SGraeme Russ 
166fea25720SGraeme Russ void __attribute__ ((regparm(0))) generate_gpf(void);
167fea25720SGraeme Russ 
168fea25720SGraeme Russ /* segment 0x70 is an arbitrary segment which does not exist */
169fea25720SGraeme Russ asm(".globl generate_gpf\n"
170fea25720SGraeme Russ 	".hidden generate_gpf\n"
171fea25720SGraeme Russ 	".type generate_gpf, @function\n"
172fea25720SGraeme Russ 	"generate_gpf:\n"
173fea25720SGraeme Russ 	"ljmp   $0x70, $0x47114711\n");
174fea25720SGraeme Russ 
175fea25720SGraeme Russ void __reset_cpu(ulong addr)
176fea25720SGraeme Russ {
177fea25720SGraeme Russ 	printf("Resetting using x86 Triple Fault\n");
178fea25720SGraeme Russ 	set_vector(13, generate_gpf);	/* general protection fault handler */
179fea25720SGraeme Russ 	set_vector(8, generate_gpf);	/* double fault handler */
180fea25720SGraeme Russ 	generate_gpf();			/* start the show */
181fea25720SGraeme Russ }
182fea25720SGraeme Russ void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
183