1*da3363d5SSimon Glass /*
2*da3363d5SSimon Glass * Copyright (C) 2011 The Chromium Authors
3*da3363d5SSimon Glass *
4*da3363d5SSimon Glass * SPDX-License-Identifier: GPL-2.0
5*da3363d5SSimon Glass */
6*da3363d5SSimon Glass
7*da3363d5SSimon Glass #include <common.h>
8*da3363d5SSimon Glass #include <dm.h>
9*da3363d5SSimon Glass #include <asm/io.h>
10*da3363d5SSimon Glass #include <asm/arch/iomap.h>
11*da3363d5SSimon Glass #include <asm/arch/pch.h>
12*da3363d5SSimon Glass
broadwell_northbridge_early_init(struct udevice * dev)13*da3363d5SSimon Glass static int broadwell_northbridge_early_init(struct udevice *dev)
14*da3363d5SSimon Glass {
15*da3363d5SSimon Glass /* Move earlier? */
16*da3363d5SSimon Glass dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
17*da3363d5SSimon Glass /* 64MiB - 0-63 buses */
18*da3363d5SSimon Glass dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
19*da3363d5SSimon Glass
20*da3363d5SSimon Glass dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
21*da3363d5SSimon Glass dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
22*da3363d5SSimon Glass dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
23*da3363d5SSimon Glass writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
24*da3363d5SSimon Glass writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
25*da3363d5SSimon Glass
26*da3363d5SSimon Glass /* Set C0000-FFFFF to access RAM on both reads and writes */
27*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM0, 0x30);
28*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM1, 0x33);
29*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM2, 0x33);
30*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM3, 0x33);
31*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM4, 0x33);
32*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM5, 0x33);
33*da3363d5SSimon Glass dm_pci_write_config8(dev, PAM6, 0x33);
34*da3363d5SSimon Glass
35*da3363d5SSimon Glass /* Device enable: IGD and Mini-HD */
36*da3363d5SSimon Glass dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
37*da3363d5SSimon Glass
38*da3363d5SSimon Glass return 0;
39*da3363d5SSimon Glass }
40*da3363d5SSimon Glass
broadwell_northbridge_probe(struct udevice * dev)41*da3363d5SSimon Glass static int broadwell_northbridge_probe(struct udevice *dev)
42*da3363d5SSimon Glass {
43*da3363d5SSimon Glass if (!(gd->flags & GD_FLG_RELOC))
44*da3363d5SSimon Glass return broadwell_northbridge_early_init(dev);
45*da3363d5SSimon Glass
46*da3363d5SSimon Glass return 0;
47*da3363d5SSimon Glass }
48*da3363d5SSimon Glass
49*da3363d5SSimon Glass static const struct udevice_id broadwell_northbridge_ids[] = {
50*da3363d5SSimon Glass { .compatible = "intel,broadwell-northbridge" },
51*da3363d5SSimon Glass { }
52*da3363d5SSimon Glass };
53*da3363d5SSimon Glass
54*da3363d5SSimon Glass U_BOOT_DRIVER(broadwell_northbridge_drv) = {
55*da3363d5SSimon Glass .name = "broadwell_northbridge",
56*da3363d5SSimon Glass .id = UCLASS_NORTHBRIDGE,
57*da3363d5SSimon Glass .of_match = broadwell_northbridge_ids,
58*da3363d5SSimon Glass .probe = broadwell_northbridge_probe,
59*da3363d5SSimon Glass };
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