1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SUPPORT_SPL 36 select SPL 37 select SPL_SEPARATE_BSS 38 help 39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 40 experimental and many features are missing. U-Boot SPL starts up, 41 runs through the 16-bit and 32-bit init, then switches to 64-bit 42 mode and jumps to U-Boot proper. 43 44endchoice 45 46config X86_64 47 bool 48 49config SPL_X86_64 50 bool 51 depends on SPL 52 53choice 54 prompt "Mainboard vendor" 55 default VENDOR_EMULATION 56 57config VENDOR_ADVANTECH 58 bool "advantech" 59 60config VENDOR_CONGATEC 61 bool "congatec" 62 63config VENDOR_COREBOOT 64 bool "coreboot" 65 66config VENDOR_DFI 67 bool "dfi" 68 69config VENDOR_EFI 70 bool "efi" 71 72config VENDOR_EMULATION 73 bool "emulation" 74 75config VENDOR_GOOGLE 76 bool "Google" 77 78config VENDOR_INTEL 79 bool "Intel" 80 81endchoice 82 83# subarchitectures-specific options below 84config INTEL_MID 85 bool "Intel MID platform support" 86 help 87 Select to build a U-Boot capable of supporting Intel MID 88 (Mobile Internet Device) platform systems which do not have 89 the PCI legacy interfaces. 90 91 If you are building for a PC class system say N here. 92 93 Intel MID platforms are based on an Intel processor and 94 chipset which consume less power than most of the x86 95 derivatives. 96 97# board-specific options below 98source "board/advantech/Kconfig" 99source "board/congatec/Kconfig" 100source "board/coreboot/Kconfig" 101source "board/dfi/Kconfig" 102source "board/efi/Kconfig" 103source "board/emulation/Kconfig" 104source "board/google/Kconfig" 105source "board/intel/Kconfig" 106 107# platform-specific options below 108source "arch/x86/cpu/baytrail/Kconfig" 109source "arch/x86/cpu/broadwell/Kconfig" 110source "arch/x86/cpu/coreboot/Kconfig" 111source "arch/x86/cpu/ivybridge/Kconfig" 112source "arch/x86/cpu/qemu/Kconfig" 113source "arch/x86/cpu/quark/Kconfig" 114source "arch/x86/cpu/queensbay/Kconfig" 115 116# architecture-specific options below 117 118config AHCI 119 default y 120 121config SYS_MALLOC_F_LEN 122 default 0x800 123 124config RAMBASE 125 hex 126 default 0x100000 127 128config XIP_ROM_SIZE 129 hex 130 depends on X86_RESET_VECTOR 131 default ROM_SIZE 132 133config CPU_ADDR_BITS 134 int 135 default 36 136 137config HPET_ADDRESS 138 hex 139 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 140 141config SMM_TSEG 142 bool 143 default n 144 145config SMM_TSEG_SIZE 146 hex 147 148config X86_RESET_VECTOR 149 bool 150 default n 151 152# The following options control where the 16-bit and 32-bit init lies 153# If SPL is enabled then it normally holds this init code, and U-Boot proper 154# is normally a 64-bit build. 155# 156# The 16-bit init refers to the reset vector and the small amount of code to 157# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 158# or missing altogether if U-Boot is started from EFI or coreboot. 159# 160# The 32-bit init refers to processor init, running binary blobs including 161# FSP, setting up interrupts and anything else that needs to be done in 162# 32-bit code. It is normally in the same place as 16-bit init if that is 163# enabled (i.e. they are both in SPL, or both in U-Boot proper). 164config X86_16BIT_INIT 165 bool 166 depends on X86_RESET_VECTOR 167 default y if X86_RESET_VECTOR && !SPL 168 help 169 This is enabled when 16-bit init is in U-Boot proper 170 171config SPL_X86_16BIT_INIT 172 bool 173 depends on X86_RESET_VECTOR 174 default y if X86_RESET_VECTOR && SPL 175 help 176 This is enabled when 16-bit init is in SPL 177 178config X86_32BIT_INIT 179 bool 180 depends on X86_RESET_VECTOR 181 default y if X86_RESET_VECTOR && !SPL 182 help 183 This is enabled when 32-bit init is in U-Boot proper 184 185config SPL_X86_32BIT_INIT 186 bool 187 depends on X86_RESET_VECTOR 188 default y if X86_RESET_VECTOR && SPL 189 help 190 This is enabled when 32-bit init is in SPL 191 192config RESET_SEG_START 193 hex 194 depends on X86_RESET_VECTOR 195 default 0xffff0000 196 197config RESET_SEG_SIZE 198 hex 199 depends on X86_RESET_VECTOR 200 default 0x10000 201 202config RESET_VEC_LOC 203 hex 204 depends on X86_RESET_VECTOR 205 default 0xfffffff0 206 207config SYS_X86_START16 208 hex 209 depends on X86_RESET_VECTOR 210 default 0xfffff800 211 212config X86_LOAD_FROM_32_BIT 213 bool "Boot from a 32-bit program" 214 help 215 Define this to boot U-Boot from a 32-bit program which sets 216 the GDT differently. This can be used to boot directly from 217 any stage of coreboot, for example, bypassing the normal 218 payload-loading feature. 219 220config BOARD_ROMSIZE_KB_512 221 bool 222config BOARD_ROMSIZE_KB_1024 223 bool 224config BOARD_ROMSIZE_KB_2048 225 bool 226config BOARD_ROMSIZE_KB_4096 227 bool 228config BOARD_ROMSIZE_KB_8192 229 bool 230config BOARD_ROMSIZE_KB_16384 231 bool 232 233choice 234 prompt "ROM chip size" 235 depends on X86_RESET_VECTOR 236 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 237 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 238 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 239 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 240 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 241 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 242 help 243 Select the size of the ROM chip you intend to flash U-Boot on. 244 245 The build system will take care of creating a u-boot.rom file 246 of the matching size. 247 248config UBOOT_ROMSIZE_KB_512 249 bool "512 KB" 250 help 251 Choose this option if you have a 512 KB ROM chip. 252 253config UBOOT_ROMSIZE_KB_1024 254 bool "1024 KB (1 MB)" 255 help 256 Choose this option if you have a 1024 KB (1 MB) ROM chip. 257 258config UBOOT_ROMSIZE_KB_2048 259 bool "2048 KB (2 MB)" 260 help 261 Choose this option if you have a 2048 KB (2 MB) ROM chip. 262 263config UBOOT_ROMSIZE_KB_4096 264 bool "4096 KB (4 MB)" 265 help 266 Choose this option if you have a 4096 KB (4 MB) ROM chip. 267 268config UBOOT_ROMSIZE_KB_8192 269 bool "8192 KB (8 MB)" 270 help 271 Choose this option if you have a 8192 KB (8 MB) ROM chip. 272 273config UBOOT_ROMSIZE_KB_16384 274 bool "16384 KB (16 MB)" 275 help 276 Choose this option if you have a 16384 KB (16 MB) ROM chip. 277 278endchoice 279 280# Map the config names to an integer (KB). 281config UBOOT_ROMSIZE_KB 282 int 283 default 512 if UBOOT_ROMSIZE_KB_512 284 default 1024 if UBOOT_ROMSIZE_KB_1024 285 default 2048 if UBOOT_ROMSIZE_KB_2048 286 default 4096 if UBOOT_ROMSIZE_KB_4096 287 default 8192 if UBOOT_ROMSIZE_KB_8192 288 default 16384 if UBOOT_ROMSIZE_KB_16384 289 290# Map the config names to a hex value (bytes). 291config ROM_SIZE 292 hex 293 default 0x80000 if UBOOT_ROMSIZE_KB_512 294 default 0x100000 if UBOOT_ROMSIZE_KB_1024 295 default 0x200000 if UBOOT_ROMSIZE_KB_2048 296 default 0x400000 if UBOOT_ROMSIZE_KB_4096 297 default 0x800000 if UBOOT_ROMSIZE_KB_8192 298 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 299 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 300 301config HAVE_INTEL_ME 302 bool "Platform requires Intel Management Engine" 303 help 304 Newer higher-end devices have an Intel Management Engine (ME) 305 which is a very large binary blob (typically 1.5MB) which is 306 required for the platform to work. This enforces a particular 307 SPI flash format. You will need to supply the me.bin file in 308 your board directory. 309 310config X86_RAMTEST 311 bool "Perform a simple RAM test after SDRAM initialisation" 312 help 313 If there is something wrong with SDRAM then the platform will 314 often crash within U-Boot or the kernel. This option enables a 315 very simple RAM test that quickly checks whether the SDRAM seems 316 to work correctly. It is not exhaustive but can save time by 317 detecting obvious failures. 318 319config FLASH_DESCRIPTOR_FILE 320 string "Flash descriptor binary filename" 321 depends on HAVE_INTEL_ME 322 default "descriptor.bin" 323 help 324 The filename of the file to use as flash descriptor in the 325 board directory. 326 327config INTEL_ME_FILE 328 string "Intel Management Engine binary filename" 329 depends on HAVE_INTEL_ME 330 default "me.bin" 331 help 332 The filename of the file to use as Intel Management Engine in the 333 board directory. 334 335config HAVE_FSP 336 bool "Add an Firmware Support Package binary" 337 depends on !EFI 338 help 339 Select this option to add an Firmware Support Package binary to 340 the resulting U-Boot image. It is a binary blob which U-Boot uses 341 to set up SDRAM and other chipset specific initialization. 342 343 Note: Without this binary U-Boot will not be able to set up its 344 SDRAM so will not boot. 345 346config FSP_FILE 347 string "Firmware Support Package binary filename" 348 depends on HAVE_FSP 349 default "fsp.bin" 350 help 351 The filename of the file to use as Firmware Support Package binary 352 in the board directory. 353 354config FSP_ADDR 355 hex "Firmware Support Package binary location" 356 depends on HAVE_FSP 357 default 0xfffc0000 358 help 359 FSP is not Position Independent Code (PIC) and the whole FSP has to 360 be rebased if it is placed at a location which is different from the 361 perferred base address specified during the FSP build. Use Intel's 362 Binary Configuration Tool (BCT) to do the rebase. 363 364 The default base address of 0xfffc0000 indicates that the binary must 365 be located at offset 0xc0000 from the beginning of a 1MB flash device. 366 367config FSP_TEMP_RAM_ADDR 368 hex 369 depends on HAVE_FSP 370 default 0x2000000 371 help 372 Stack top address which is used in fsp_init() after DRAM is ready and 373 CAR is disabled. 374 375config FSP_SYS_MALLOC_F_LEN 376 hex 377 depends on HAVE_FSP 378 default 0x100000 379 help 380 Additional size of malloc() pool before relocation. 381 382config FSP_USE_UPD 383 bool 384 depends on HAVE_FSP 385 default y 386 help 387 Most FSPs use UPD data region for some FSP customization. But there 388 are still some FSPs that might not even have UPD. For such FSPs, 389 override this to n in their platform Kconfig files. 390 391config FSP_BROKEN_HOB 392 bool 393 depends on HAVE_FSP 394 help 395 Indicate some buggy FSPs that does not report memory used by FSP 396 itself as reserved in the resource descriptor HOB. Select this to 397 tell U-Boot to do some additional work to ensure U-Boot relocation 398 do not overwrite the important boot service data which is used by 399 FSP, otherwise the subsequent call to fsp_notify() will fail. 400 401config ENABLE_MRC_CACHE 402 bool "Enable MRC cache" 403 depends on !EFI && !SYS_COREBOOT 404 help 405 Enable this feature to cause MRC data to be cached in NV storage 406 to be used for speeding up boot time on future reboots and/or 407 power cycles. 408 409 For platforms that use Intel FSP for the memory initialization, 410 please check FSP output HOB via U-Boot command 'fsp hob' to see 411 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 412 If such GUID does not exist, MRC cache is not avaiable on such 413 platform (eg: Intel Queensbay), which means selecting this option 414 here does not make any difference. 415 416config HAVE_MRC 417 bool "Add a System Agent binary" 418 depends on !HAVE_FSP 419 help 420 Select this option to add a System Agent binary to 421 the resulting U-Boot image. MRC stands for Memory Reference Code. 422 It is a binary blob which U-Boot uses to set up SDRAM. 423 424 Note: Without this binary U-Boot will not be able to set up its 425 SDRAM so will not boot. 426 427config CACHE_MRC_BIN 428 bool 429 depends on HAVE_MRC 430 default n 431 help 432 Enable caching for the memory reference code binary. This uses an 433 MTRR (memory type range register) to turn on caching for the section 434 of SPI flash that contains the memory reference code. This makes 435 SDRAM init run faster. 436 437config CACHE_MRC_SIZE_KB 438 int 439 depends on HAVE_MRC 440 default 512 441 help 442 Sets the size of the cached area for the memory reference code. 443 This ends at the end of SPI flash (address 0xffffffff) and is 444 measured in KB. Typically this is set to 512, providing for 0.5MB 445 of cached space. 446 447config DCACHE_RAM_BASE 448 hex 449 depends on HAVE_MRC 450 help 451 Sets the base of the data cache area in memory space. This is the 452 start address of the cache-as-RAM (CAR) area and the address varies 453 depending on the CPU. Once CAR is set up, read/write memory becomes 454 available at this address and can be used temporarily until SDRAM 455 is working. 456 457config DCACHE_RAM_SIZE 458 hex 459 depends on HAVE_MRC 460 default 0x40000 461 help 462 Sets the total size of the data cache area in memory space. This 463 sets the size of the cache-as-RAM (CAR) area. Note that much of the 464 CAR space is required by the MRC. The CAR space available to U-Boot 465 is normally at the start and typically extends to 1/4 or 1/2 of the 466 available size. 467 468config DCACHE_RAM_MRC_VAR_SIZE 469 hex 470 depends on HAVE_MRC 471 help 472 This is the amount of CAR (Cache as RAM) reserved for use by the 473 memory reference code. This depends on the implementation of the 474 memory reference code and must be set correctly or the board will 475 not boot. 476 477config HAVE_REFCODE 478 bool "Add a Reference Code binary" 479 help 480 Select this option to add a Reference Code binary to the resulting 481 U-Boot image. This is an Intel binary blob that handles system 482 initialisation, in this case the PCH and System Agent. 483 484 Note: Without this binary (on platforms that need it such as 485 broadwell) U-Boot will be missing some critical setup steps. 486 Various peripherals may fail to work. 487 488config SMP 489 bool "Enable Symmetric Multiprocessing" 490 default n 491 help 492 Enable use of more than one CPU in U-Boot and the Operating System 493 when loaded. Each CPU will be started up and information can be 494 obtained using the 'cpu' command. If this option is disabled, then 495 only one CPU will be enabled regardless of the number of CPUs 496 available. 497 498config MAX_CPUS 499 int "Maximum number of CPUs permitted" 500 depends on SMP 501 default 4 502 help 503 When using multi-CPU chips it is possible for U-Boot to start up 504 more than one CPU. The stack memory used by all of these CPUs is 505 pre-allocated so at present U-Boot wants to know the maximum 506 number of CPUs that may be present. Set this to at least as high 507 as the number of CPUs in your system (it uses about 4KB of RAM for 508 each CPU). 509 510config AP_STACK_SIZE 511 hex 512 depends on SMP 513 default 0x1000 514 help 515 Each additional CPU started by U-Boot requires its own stack. This 516 option sets the stack size used by each CPU and directly affects 517 the memory used by this initialisation process. Typically 4KB is 518 enough space. 519 520config HAVE_VGA_BIOS 521 bool "Add a VGA BIOS image" 522 help 523 Select this option if you have a VGA BIOS image that you would 524 like to add to your ROM. 525 526config VGA_BIOS_FILE 527 string "VGA BIOS image filename" 528 depends on HAVE_VGA_BIOS 529 default "vga.bin" 530 help 531 The filename of the VGA BIOS image in the board directory. 532 533config VGA_BIOS_ADDR 534 hex "VGA BIOS image location" 535 depends on HAVE_VGA_BIOS 536 default 0xfff90000 537 help 538 The location of VGA BIOS image in the SPI flash. For example, base 539 address of 0xfff90000 indicates that the image will be put at offset 540 0x90000 from the beginning of a 1MB flash device. 541 542menu "System tables" 543 depends on !EFI && !SYS_COREBOOT 544 545config GENERATE_PIRQ_TABLE 546 bool "Generate a PIRQ table" 547 default n 548 help 549 Generate a PIRQ routing table for this board. The PIRQ routing table 550 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 551 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 552 It specifies the interrupt router information as well how all the PCI 553 devices' interrupt pins are wired to PIRQs. 554 555config GENERATE_SFI_TABLE 556 bool "Generate a SFI (Simple Firmware Interface) table" 557 help 558 The Simple Firmware Interface (SFI) provides a lightweight method 559 for platform firmware to pass information to the operating system 560 via static tables in memory. Kernel SFI support is required to 561 boot on SFI-only platforms. If you have ACPI tables then these are 562 used instead. 563 564 U-Boot writes this table in write_sfi_table() just before booting 565 the OS. 566 567 For more information, see http://simplefirmware.org 568 569config GENERATE_MP_TABLE 570 bool "Generate an MP (Multi-Processor) table" 571 default n 572 help 573 Generate an MP (Multi-Processor) table for this board. The MP table 574 provides a way for the operating system to support for symmetric 575 multiprocessing as well as symmetric I/O interrupt handling with 576 the local APIC and I/O APIC. 577 578config GENERATE_ACPI_TABLE 579 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 580 default n 581 select QFW if QEMU 582 help 583 The Advanced Configuration and Power Interface (ACPI) specification 584 provides an open standard for device configuration and management 585 by the operating system. It defines platform-independent interfaces 586 for configuration and power management monitoring. 587 588endmenu 589 590config MAX_PIRQ_LINKS 591 int 592 default 8 593 help 594 This variable specifies the number of PIRQ interrupt links which are 595 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 596 Some newer chipsets offer more than four links, commonly up to PIRQH. 597 598config IRQ_SLOT_COUNT 599 int 600 default 128 601 help 602 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 603 which in turns forms a table of exact 4KiB. The default value 128 604 should be enough for most boards. If this does not fit your board, 605 change it according to your needs. 606 607config PCIE_ECAM_BASE 608 hex 609 default 0xe0000000 610 help 611 This is the memory-mapped address of PCI configuration space, which 612 is only available through the Enhanced Configuration Access 613 Mechanism (ECAM) with PCI Express. It can be set up almost 614 anywhere. Before it is set up, it is possible to access PCI 615 configuration space through I/O access, but memory access is more 616 convenient. Using this, PCI can be scanned and configured. This 617 should be set to a region that does not conflict with memory 618 assigned to PCI devices - i.e. the memory and prefetch regions, as 619 passed to pci_set_region(). 620 621config PCIE_ECAM_SIZE 622 hex 623 default 0x10000000 624 help 625 This is the size of memory-mapped address of PCI configuration space, 626 which is only available through the Enhanced Configuration Access 627 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 628 so a default 0x10000000 size covers all of the 256 buses which is the 629 maximum number of PCI buses as defined by the PCI specification. 630 631config I8259_PIC 632 bool 633 default y 634 help 635 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 636 slave) interrupt controllers. Include this to have U-Boot set up 637 the interrupt correctly. 638 639config I8254_TIMER 640 bool 641 default y 642 help 643 Intel 8254 timer contains three counters which have fixed uses. 644 Include this to have U-Boot set up the timer correctly. 645 646config SEABIOS 647 bool "Support booting SeaBIOS" 648 help 649 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 650 It can run in an emulator or natively on X86 hardware with the use 651 of coreboot/U-Boot. By turning on this option, U-Boot prepares 652 all the configuration tables that are necessary to boot SeaBIOS. 653 654 Check http://www.seabios.org/SeaBIOS for details. 655 656config HIGH_TABLE_SIZE 657 hex "Size of configuration tables which reside in high memory" 658 default 0x10000 659 depends on SEABIOS 660 help 661 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 662 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 663 puts a copy of configuration tables in high memory region which 664 is reserved on the stack before relocation. The region size is 665 determined by this option. 666 667 Increse it if the default size does not fit the board's needs. 668 This is most likely due to a large ACPI DSDT table is used. 669 670source "arch/x86/lib/efi/Kconfig" 671 672endmenu 673