xref: /rk3399_rockchip-uboot/arch/x86/Kconfig (revision a274e9cac55de3c8ca4e877912a260fb646df38d) 
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7config USE_PRIVATE_LIBGCC
8	default y
9
10choice
11	prompt "Target select"
12
13config TARGET_COREBOOT
14	bool "Support coreboot"
15	help
16	  This target is used for running U-Boot on top of Coreboot. In
17	  this case Coreboot does the early inititalisation, and U-Boot
18	  takes over once the RAM, video and CPU are fully running.
19	  U-Boot is loaded as a fallback payload from Coreboot, in
20	  Coreboot terminology. This method was used for the Chromebook
21	  Pixel when launched.
22
23config TARGET_CHROMEBOOK_LINK
24	bool "Support Chromebook link"
25	help
26	  This is the Chromebook Pixel released in 2013. It uses an Intel
27	  i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28	  SDRAM. It has a Panther Point platform controller hub, PCIe
29	  WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30	  reader, microphone and speakers, display port and 32GB SATA
31	  solid state drive. There is a Chrome OS EC connected on LPC,
32	  and it provides a 2560x1700 high resolution touch-enabled LCD
33	  display.
34
35config TARGET_CHROMEBOX_PANTHER
36	bool "Support Chromebox panther (not available)"
37	select n
38	help
39	  Note: At present this must be used with Coreboot. See README.x86
40	  for instructions.
41
42	  This is the Asus Chromebox CN60 released in 2014. It uses an Intel
43	  Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
44	  Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
45	  includes a USB SD reader, four USB3 ports, display port and HDMI
46	  video output and a 16GB SATA solid state drive. There is no Chrome
47	  OS EC on this model.
48
49config TARGET_CROWNBAY
50	bool "Support Intel Crown Bay CRB"
51	help
52	  This is the Intel Crown Bay Customer Reference Board. It contains
53	  the Intel Atom Processor E6xx populated on the COM Express module
54	  with 1GB DDR2 soldered down memory and a carrier board with the
55	  Intel Platform Controller Hub EG20T, other system components and
56	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
57
58config TARGET_MINNOWMAX
59	bool "Support Intel Minnowboard MAX"
60	help
61	  This is the Intel Minnowboard MAX. It contains an Atom E3800
62	  processor in a small form factor with Ethernet, micro-SD, USB 2,
63	  USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
64	  It requires some binary blobs - see README.x86 for details.
65
66	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
67	  by U-Boot matches that value.
68
69config TARGET_GALILEO
70	bool "Support Intel Galileo"
71	help
72	  This is the Intel Galileo board, which is the first in a family of
73	  Arduino-certified development and prototyping boards based on Intel
74	  architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
75	  single-core, single-thread, Intel Pentium processor instrunction set
76	  architecture (ISA) compatible, operating at speeds up to 400Mhz,
77	  along with 256MB DDR3 memory. It supports a wide range of industry
78	  standard I/O interfaces, including a full-sized mini-PCIe slot,
79	  one 100Mb Ethernet port, a microSD card slot, a USB host port and
80	  a USB client port.
81
82endchoice
83
84config DM
85	default y
86
87config DM_GPIO
88	default y
89
90config DM_SERIAL
91	default y
92
93config DM_SERIAL
94 	default y
95
96config DM_SPI
97	default y
98
99config DM_SPI_FLASH
100	default y
101
102config SYS_MALLOC_F_LEN
103	default 0x800
104
105config RAMBASE
106	hex
107	default 0x100000
108
109config XIP_ROM_SIZE
110	hex
111	depends on X86_RESET_VECTOR
112	default ROM_SIZE
113
114config CPU_ADDR_BITS
115	int
116	default 36
117
118config HPET_ADDRESS
119	hex
120	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
121
122config SMM_TSEG
123	bool
124	default n
125
126config SMM_TSEG_SIZE
127	hex
128
129config X86_RESET_VECTOR
130	bool
131	default n
132
133config SYS_X86_START16
134	hex
135	depends on X86_RESET_VECTOR
136	default 0xfffff800
137
138config BOARD_ROMSIZE_KB_512
139	bool
140config BOARD_ROMSIZE_KB_1024
141	bool
142config BOARD_ROMSIZE_KB_2048
143	bool
144config BOARD_ROMSIZE_KB_4096
145	bool
146config BOARD_ROMSIZE_KB_8192
147	bool
148config BOARD_ROMSIZE_KB_16384
149	bool
150
151choice
152	prompt "ROM chip size"
153	depends on X86_RESET_VECTOR
154	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
155	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
156	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
157	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
158	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
159	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
160	help
161	  Select the size of the ROM chip you intend to flash U-Boot on.
162
163	  The build system will take care of creating a u-boot.rom file
164	  of the matching size.
165
166config UBOOT_ROMSIZE_KB_512
167	bool "512 KB"
168	help
169	  Choose this option if you have a 512 KB ROM chip.
170
171config UBOOT_ROMSIZE_KB_1024
172	bool "1024 KB (1 MB)"
173	help
174	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
175
176config UBOOT_ROMSIZE_KB_2048
177	bool "2048 KB (2 MB)"
178	help
179	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
180
181config UBOOT_ROMSIZE_KB_4096
182	bool "4096 KB (4 MB)"
183	help
184	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
185
186config UBOOT_ROMSIZE_KB_8192
187	bool "8192 KB (8 MB)"
188	help
189	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
190
191config UBOOT_ROMSIZE_KB_16384
192	bool "16384 KB (16 MB)"
193	help
194	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
195
196endchoice
197
198# Map the config names to an integer (KB).
199config UBOOT_ROMSIZE_KB
200	int
201	default 512 if UBOOT_ROMSIZE_KB_512
202	default 1024 if UBOOT_ROMSIZE_KB_1024
203	default 2048 if UBOOT_ROMSIZE_KB_2048
204	default 4096 if UBOOT_ROMSIZE_KB_4096
205	default 8192 if UBOOT_ROMSIZE_KB_8192
206	default 16384 if UBOOT_ROMSIZE_KB_16384
207
208# Map the config names to a hex value (bytes).
209config ROM_SIZE
210	hex
211	default 0x80000 if UBOOT_ROMSIZE_KB_512
212	default 0x100000 if UBOOT_ROMSIZE_KB_1024
213	default 0x200000 if UBOOT_ROMSIZE_KB_2048
214	default 0x400000 if UBOOT_ROMSIZE_KB_4096
215	default 0x800000 if UBOOT_ROMSIZE_KB_8192
216	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
217	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
218
219config HAVE_INTEL_ME
220	bool "Platform requires Intel Management Engine"
221	help
222	  Newer higher-end devices have an Intel Management Engine (ME)
223	  which is a very large binary blob (typically 1.5MB) which is
224	  required for the platform to work. This enforces a particular
225	  SPI flash format. You will need to supply the me.bin file in
226	  your board directory.
227
228config X86_RAMTEST
229	bool "Perform a simple RAM test after SDRAM initialisation"
230	help
231	  If there is something wrong with SDRAM then the platform will
232	  often crash within U-Boot or the kernel. This option enables a
233	  very simple RAM test that quickly checks whether the SDRAM seems
234	  to work correctly. It is not exhaustive but can save time by
235	  detecting obvious failures.
236
237config MARK_GRAPHICS_MEM_WRCOMB
238	bool "Mark graphics memory as write-combining."
239	default n
240	help
241	 The graphics performance may increase if the graphics
242	 memory is set as write-combining cache type. This option
243	 enables marking the graphics memory as write-combining.
244
245menu "Display"
246
247config FRAMEBUFFER_SET_VESA_MODE
248	prompt "Set framebuffer graphics resolution"
249	bool
250	help
251	  Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
252
253choice
254	prompt "framebuffer graphics resolution"
255	default FRAMEBUFFER_VESA_MODE_117
256	depends on FRAMEBUFFER_SET_VESA_MODE
257	help
258	  This option sets the resolution used for the coreboot framebuffer (and
259	  bootsplash screen).
260
261config FRAMEBUFFER_VESA_MODE_100
262	bool "640x400 256-color"
263
264config FRAMEBUFFER_VESA_MODE_101
265	bool "640x480 256-color"
266
267config FRAMEBUFFER_VESA_MODE_102
268	bool "800x600 16-color"
269
270config FRAMEBUFFER_VESA_MODE_103
271	bool "800x600 256-color"
272
273config FRAMEBUFFER_VESA_MODE_104
274	bool "1024x768 16-color"
275
276config FRAMEBUFFER_VESA_MODE_105
277	bool "1024x7686 256-color"
278
279config FRAMEBUFFER_VESA_MODE_106
280	bool "1280x1024 16-color"
281
282config FRAMEBUFFER_VESA_MODE_107
283	bool "1280x1024 256-color"
284
285config FRAMEBUFFER_VESA_MODE_108
286	bool "80x60 text"
287
288config FRAMEBUFFER_VESA_MODE_109
289	bool "132x25 text"
290
291config FRAMEBUFFER_VESA_MODE_10A
292	bool "132x43 text"
293
294config FRAMEBUFFER_VESA_MODE_10B
295	bool "132x50 text"
296
297config FRAMEBUFFER_VESA_MODE_10C
298	bool "132x60 text"
299
300config FRAMEBUFFER_VESA_MODE_10D
301	bool "320x200 32k-color (1:5:5:5)"
302
303config FRAMEBUFFER_VESA_MODE_10E
304	bool "320x200 64k-color (5:6:5)"
305
306config FRAMEBUFFER_VESA_MODE_10F
307	bool "320x200 16.8M-color (8:8:8)"
308
309config FRAMEBUFFER_VESA_MODE_110
310	bool "640x480 32k-color (1:5:5:5)"
311
312config FRAMEBUFFER_VESA_MODE_111
313	bool "640x480 64k-color (5:6:5)"
314
315config FRAMEBUFFER_VESA_MODE_112
316	bool "640x480 16.8M-color (8:8:8)"
317
318config FRAMEBUFFER_VESA_MODE_113
319	bool "800x600 32k-color (1:5:5:5)"
320
321config FRAMEBUFFER_VESA_MODE_114
322	bool "800x600 64k-color (5:6:5)"
323
324config FRAMEBUFFER_VESA_MODE_115
325	bool "800x600 16.8M-color (8:8:8)"
326
327config FRAMEBUFFER_VESA_MODE_116
328	bool "1024x768 32k-color (1:5:5:5)"
329
330config FRAMEBUFFER_VESA_MODE_117
331	bool "1024x768 64k-color (5:6:5)"
332
333config FRAMEBUFFER_VESA_MODE_118
334	bool "1024x768 16.8M-color (8:8:8)"
335
336config FRAMEBUFFER_VESA_MODE_119
337	bool "1280x1024 32k-color (1:5:5:5)"
338
339config FRAMEBUFFER_VESA_MODE_11A
340	bool "1280x1024 64k-color (5:6:5)"
341
342config FRAMEBUFFER_VESA_MODE_11B
343	bool "1280x1024 16.8M-color (8:8:8)"
344
345config FRAMEBUFFER_VESA_MODE_USER
346	bool "Manually select VESA mode"
347
348endchoice
349
350# Map the config names to an integer (KB).
351config FRAMEBUFFER_VESA_MODE
352	prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
353	hex
354	default 0x100 if FRAMEBUFFER_VESA_MODE_100
355	default 0x101 if FRAMEBUFFER_VESA_MODE_101
356	default 0x102 if FRAMEBUFFER_VESA_MODE_102
357	default 0x103 if FRAMEBUFFER_VESA_MODE_103
358	default 0x104 if FRAMEBUFFER_VESA_MODE_104
359	default 0x105 if FRAMEBUFFER_VESA_MODE_105
360	default 0x106 if FRAMEBUFFER_VESA_MODE_106
361	default 0x107 if FRAMEBUFFER_VESA_MODE_107
362	default 0x108 if FRAMEBUFFER_VESA_MODE_108
363	default 0x109 if FRAMEBUFFER_VESA_MODE_109
364	default 0x10A if FRAMEBUFFER_VESA_MODE_10A
365	default 0x10B if FRAMEBUFFER_VESA_MODE_10B
366	default 0x10C if FRAMEBUFFER_VESA_MODE_10C
367	default 0x10D if FRAMEBUFFER_VESA_MODE_10D
368	default 0x10E if FRAMEBUFFER_VESA_MODE_10E
369	default 0x10F if FRAMEBUFFER_VESA_MODE_10F
370	default 0x110 if FRAMEBUFFER_VESA_MODE_110
371	default 0x111 if FRAMEBUFFER_VESA_MODE_111
372	default 0x112 if FRAMEBUFFER_VESA_MODE_112
373	default 0x113 if FRAMEBUFFER_VESA_MODE_113
374	default 0x114 if FRAMEBUFFER_VESA_MODE_114
375	default 0x115 if FRAMEBUFFER_VESA_MODE_115
376	default 0x116 if FRAMEBUFFER_VESA_MODE_116
377	default 0x117 if FRAMEBUFFER_VESA_MODE_117
378	default 0x118 if FRAMEBUFFER_VESA_MODE_118
379	default 0x119 if FRAMEBUFFER_VESA_MODE_119
380	default 0x11A if FRAMEBUFFER_VESA_MODE_11A
381	default 0x11B if FRAMEBUFFER_VESA_MODE_11B
382	default 0x117 if FRAMEBUFFER_VESA_MODE_USER
383
384endmenu
385
386config HAVE_FSP
387	bool "Add an Firmware Support Package binary"
388	help
389	  Select this option to add an Firmware Support Package binary to
390	  the resulting U-Boot image. It is a binary blob which U-Boot uses
391	  to set up SDRAM and other chipset specific initialization.
392
393	  Note: Without this binary U-Boot will not be able to set up its
394	  SDRAM so will not boot.
395
396config FSP_FILE
397	string "Firmware Support Package binary filename"
398	depends on HAVE_FSP
399	default "fsp.bin"
400	help
401	  The filename of the file to use as Firmware Support Package binary
402	  in the board directory.
403
404config FSP_ADDR
405	hex "Firmware Support Package binary location"
406	depends on HAVE_FSP
407	default 0xfffc0000
408	help
409	  FSP is not Position Independent Code (PIC) and the whole FSP has to
410	  be rebased if it is placed at a location which is different from the
411	  perferred base address specified during the FSP build. Use Intel's
412	  Binary Configuration Tool (BCT) to do the rebase.
413
414	  The default base address of 0xfffc0000 indicates that the binary must
415	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
416
417config FSP_TEMP_RAM_ADDR
418	hex
419	default 0x2000000
420	help
421	  Stack top address which is used in FspInit after DRAM is ready and
422	  CAR is disabled.
423
424source "arch/x86/cpu/baytrail/Kconfig"
425
426source "arch/x86/cpu/coreboot/Kconfig"
427
428source "arch/x86/cpu/ivybridge/Kconfig"
429
430source "arch/x86/cpu/quark/Kconfig"
431
432source "arch/x86/cpu/queensbay/Kconfig"
433
434config TSC_CALIBRATION_BYPASS
435	bool "Bypass Time-Stamp Counter (TSC) calibration"
436	default n
437	help
438	  By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
439	  running frequency via Model-Specific Register (MSR) and Programmable
440	  Interval Timer (PIT). If the calibration does not work on your board,
441	  select this option and provide a hardcoded TSC running frequency with
442	  CONFIG_TSC_FREQ_IN_MHZ below.
443
444	  Normally this option should be turned on in a simulation environment
445	  like qemu.
446
447config TSC_FREQ_IN_MHZ
448	int "Time-Stamp Counter (TSC) running frequency in MHz"
449	depends on TSC_CALIBRATION_BYPASS
450	default 1000
451	help
452	  The running frequency in MHz of Time-Stamp Counter (TSC).
453
454source "board/coreboot/coreboot/Kconfig"
455
456source "board/google/chromebook_link/Kconfig"
457
458source "board/google/chromebox_panther/Kconfig"
459
460source "board/intel/crownbay/Kconfig"
461
462source "board/intel/minnowmax/Kconfig"
463
464source "board/intel/galileo/Kconfig"
465
466config PCIE_ECAM_BASE
467	hex
468	default 0xe0000000
469	help
470	  This is the memory-mapped address of PCI configuration space, which
471	  is only available through the Enhanced Configuration Access
472	  Mechanism (ECAM) with PCI Express. It can be set up almost
473	  anywhere. Before it is set up, it is possible to access PCI
474	  configuration space through I/O access, but memory access is more
475	  convenient. Using this, PCI can be scanned and configured. This
476	  should be set to a region that does not conflict with memory
477	  assigned to PCI devices - i.e. the memory and prefetch regions, as
478	  passed to pci_set_region().
479
480endmenu
481