1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Mainboard vendor" 9 default VENDOR_EMULATION 10 11config VENDOR_COREBOOT 12 bool "coreboot" 13 14config VENDOR_EFI 15 bool "efi" 16 17config VENDOR_EMULATION 18 bool "emulation" 19 20config VENDOR_GOOGLE 21 bool "Google" 22 23config VENDOR_INTEL 24 bool "Intel" 25 26endchoice 27 28# board-specific options below 29source "board/coreboot/Kconfig" 30source "board/efi/Kconfig" 31source "board/emulation/Kconfig" 32source "board/google/Kconfig" 33source "board/intel/Kconfig" 34 35# platform-specific options below 36source "arch/x86/cpu/baytrail/Kconfig" 37source "arch/x86/cpu/coreboot/Kconfig" 38source "arch/x86/cpu/ivybridge/Kconfig" 39source "arch/x86/cpu/qemu/Kconfig" 40source "arch/x86/cpu/quark/Kconfig" 41source "arch/x86/cpu/queensbay/Kconfig" 42 43# architecture-specific options below 44 45config SYS_MALLOC_F_LEN 46 default 0x800 47 48config RAMBASE 49 hex 50 default 0x100000 51 52config XIP_ROM_SIZE 53 hex 54 depends on X86_RESET_VECTOR 55 default ROM_SIZE 56 57config CPU_ADDR_BITS 58 int 59 default 36 60 61config HPET_ADDRESS 62 hex 63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 64 65config SMM_TSEG 66 bool 67 default n 68 69config SMM_TSEG_SIZE 70 hex 71 72config X86_RESET_VECTOR 73 bool 74 default n 75 76config RESET_SEG_START 77 hex 78 depends on X86_RESET_VECTOR 79 default 0xffff0000 80 81config RESET_SEG_SIZE 82 hex 83 depends on X86_RESET_VECTOR 84 default 0x10000 85 86config RESET_VEC_LOC 87 hex 88 depends on X86_RESET_VECTOR 89 default 0xfffffff0 90 91config SYS_X86_START16 92 hex 93 depends on X86_RESET_VECTOR 94 default 0xfffff800 95 96config BOARD_ROMSIZE_KB_512 97 bool 98config BOARD_ROMSIZE_KB_1024 99 bool 100config BOARD_ROMSIZE_KB_2048 101 bool 102config BOARD_ROMSIZE_KB_4096 103 bool 104config BOARD_ROMSIZE_KB_8192 105 bool 106config BOARD_ROMSIZE_KB_16384 107 bool 108 109choice 110 prompt "ROM chip size" 111 depends on X86_RESET_VECTOR 112 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 113 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 114 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 115 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 116 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 117 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 118 help 119 Select the size of the ROM chip you intend to flash U-Boot on. 120 121 The build system will take care of creating a u-boot.rom file 122 of the matching size. 123 124config UBOOT_ROMSIZE_KB_512 125 bool "512 KB" 126 help 127 Choose this option if you have a 512 KB ROM chip. 128 129config UBOOT_ROMSIZE_KB_1024 130 bool "1024 KB (1 MB)" 131 help 132 Choose this option if you have a 1024 KB (1 MB) ROM chip. 133 134config UBOOT_ROMSIZE_KB_2048 135 bool "2048 KB (2 MB)" 136 help 137 Choose this option if you have a 2048 KB (2 MB) ROM chip. 138 139config UBOOT_ROMSIZE_KB_4096 140 bool "4096 KB (4 MB)" 141 help 142 Choose this option if you have a 4096 KB (4 MB) ROM chip. 143 144config UBOOT_ROMSIZE_KB_8192 145 bool "8192 KB (8 MB)" 146 help 147 Choose this option if you have a 8192 KB (8 MB) ROM chip. 148 149config UBOOT_ROMSIZE_KB_16384 150 bool "16384 KB (16 MB)" 151 help 152 Choose this option if you have a 16384 KB (16 MB) ROM chip. 153 154endchoice 155 156# Map the config names to an integer (KB). 157config UBOOT_ROMSIZE_KB 158 int 159 default 512 if UBOOT_ROMSIZE_KB_512 160 default 1024 if UBOOT_ROMSIZE_KB_1024 161 default 2048 if UBOOT_ROMSIZE_KB_2048 162 default 4096 if UBOOT_ROMSIZE_KB_4096 163 default 8192 if UBOOT_ROMSIZE_KB_8192 164 default 16384 if UBOOT_ROMSIZE_KB_16384 165 166# Map the config names to a hex value (bytes). 167config ROM_SIZE 168 hex 169 default 0x80000 if UBOOT_ROMSIZE_KB_512 170 default 0x100000 if UBOOT_ROMSIZE_KB_1024 171 default 0x200000 if UBOOT_ROMSIZE_KB_2048 172 default 0x400000 if UBOOT_ROMSIZE_KB_4096 173 default 0x800000 if UBOOT_ROMSIZE_KB_8192 174 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 175 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 176 177config HAVE_INTEL_ME 178 bool "Platform requires Intel Management Engine" 179 help 180 Newer higher-end devices have an Intel Management Engine (ME) 181 which is a very large binary blob (typically 1.5MB) which is 182 required for the platform to work. This enforces a particular 183 SPI flash format. You will need to supply the me.bin file in 184 your board directory. 185 186config X86_RAMTEST 187 bool "Perform a simple RAM test after SDRAM initialisation" 188 help 189 If there is something wrong with SDRAM then the platform will 190 often crash within U-Boot or the kernel. This option enables a 191 very simple RAM test that quickly checks whether the SDRAM seems 192 to work correctly. It is not exhaustive but can save time by 193 detecting obvious failures. 194 195config HAVE_FSP 196 bool "Add an Firmware Support Package binary" 197 help 198 Select this option to add an Firmware Support Package binary to 199 the resulting U-Boot image. It is a binary blob which U-Boot uses 200 to set up SDRAM and other chipset specific initialization. 201 202 Note: Without this binary U-Boot will not be able to set up its 203 SDRAM so will not boot. 204 205config FSP_FILE 206 string "Firmware Support Package binary filename" 207 depends on HAVE_FSP 208 default "fsp.bin" 209 help 210 The filename of the file to use as Firmware Support Package binary 211 in the board directory. 212 213config FSP_ADDR 214 hex "Firmware Support Package binary location" 215 depends on HAVE_FSP 216 default 0xfffc0000 217 help 218 FSP is not Position Independent Code (PIC) and the whole FSP has to 219 be rebased if it is placed at a location which is different from the 220 perferred base address specified during the FSP build. Use Intel's 221 Binary Configuration Tool (BCT) to do the rebase. 222 223 The default base address of 0xfffc0000 indicates that the binary must 224 be located at offset 0xc0000 from the beginning of a 1MB flash device. 225 226config FSP_TEMP_RAM_ADDR 227 hex 228 depends on HAVE_FSP 229 default 0x2000000 230 help 231 Stack top address which is used in FspInit after DRAM is ready and 232 CAR is disabled. 233 234config SMP 235 bool "Enable Symmetric Multiprocessing" 236 default n 237 help 238 Enable use of more than one CPU in U-Boot and the Operating System 239 when loaded. Each CPU will be started up and information can be 240 obtained using the 'cpu' command. If this option is disabled, then 241 only one CPU will be enabled regardless of the number of CPUs 242 available. 243 244config MAX_CPUS 245 int "Maximum number of CPUs permitted" 246 depends on SMP 247 default 4 248 help 249 When using multi-CPU chips it is possible for U-Boot to start up 250 more than one CPU. The stack memory used by all of these CPUs is 251 pre-allocated so at present U-Boot wants to know the maximum 252 number of CPUs that may be present. Set this to at least as high 253 as the number of CPUs in your system (it uses about 4KB of RAM for 254 each CPU). 255 256config AP_STACK_SIZE 257 hex 258 depends on SMP 259 default 0x1000 260 help 261 Each additional CPU started by U-Boot requires its own stack. This 262 option sets the stack size used by each CPU and directly affects 263 the memory used by this initialisation process. Typically 4KB is 264 enough space. 265 266config TSC_CALIBRATION_BYPASS 267 bool "Bypass Time-Stamp Counter (TSC) calibration" 268 default n 269 help 270 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 271 running frequency via Model-Specific Register (MSR) and Programmable 272 Interval Timer (PIT). If the calibration does not work on your board, 273 select this option and provide a hardcoded TSC running frequency with 274 CONFIG_TSC_FREQ_IN_MHZ below. 275 276 Normally this option should be turned on in a simulation environment 277 like qemu. 278 279config TSC_FREQ_IN_MHZ 280 int "Time-Stamp Counter (TSC) running frequency in MHz" 281 depends on TSC_CALIBRATION_BYPASS 282 default 1000 283 help 284 The running frequency in MHz of Time-Stamp Counter (TSC). 285 286config HAVE_VGA_BIOS 287 bool "Add a VGA BIOS image" 288 help 289 Select this option if you have a VGA BIOS image that you would 290 like to add to your ROM. 291 292config VGA_BIOS_FILE 293 string "VGA BIOS image filename" 294 depends on HAVE_VGA_BIOS 295 default "vga.bin" 296 help 297 The filename of the VGA BIOS image in the board directory. 298 299config VGA_BIOS_ADDR 300 hex "VGA BIOS image location" 301 depends on HAVE_VGA_BIOS 302 default 0xfff90000 303 help 304 The location of VGA BIOS image in the SPI flash. For example, base 305 address of 0xfff90000 indicates that the image will be put at offset 306 0x90000 from the beginning of a 1MB flash device. 307 308menu "System tables" 309 310config GENERATE_PIRQ_TABLE 311 bool "Generate a PIRQ table" 312 default n 313 help 314 Generate a PIRQ routing table for this board. The PIRQ routing table 315 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 316 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 317 It specifies the interrupt router information as well how all the PCI 318 devices' interrupt pins are wired to PIRQs. 319 320config GENERATE_SFI_TABLE 321 bool "Generate a SFI (Simple Firmware Interface) table" 322 help 323 The Simple Firmware Interface (SFI) provides a lightweight method 324 for platform firmware to pass information to the operating system 325 via static tables in memory. Kernel SFI support is required to 326 boot on SFI-only platforms. If you have ACPI tables then these are 327 used instead. 328 329 U-Boot writes this table in write_sfi_table() just before booting 330 the OS. 331 332 For more information, see http://simplefirmware.org 333 334config GENERATE_MP_TABLE 335 bool "Generate an MP (Multi-Processor) table" 336 default n 337 help 338 Generate an MP (Multi-Processor) table for this board. The MP table 339 provides a way for the operating system to support for symmetric 340 multiprocessing as well as symmetric I/O interrupt handling with 341 the local APIC and I/O APIC. 342 343endmenu 344 345config MAX_PIRQ_LINKS 346 int 347 default 8 348 help 349 This variable specifies the number of PIRQ interrupt links which are 350 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 351 Some newer chipsets offer more than four links, commonly up to PIRQH. 352 353config IRQ_SLOT_COUNT 354 int 355 default 128 356 help 357 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 358 which in turns forms a table of exact 4KiB. The default value 128 359 should be enough for most boards. If this does not fit your board, 360 change it according to your needs. 361 362config PCIE_ECAM_BASE 363 hex 364 default 0xe0000000 365 help 366 This is the memory-mapped address of PCI configuration space, which 367 is only available through the Enhanced Configuration Access 368 Mechanism (ECAM) with PCI Express. It can be set up almost 369 anywhere. Before it is set up, it is possible to access PCI 370 configuration space through I/O access, but memory access is more 371 convenient. Using this, PCI can be scanned and configured. This 372 should be set to a region that does not conflict with memory 373 assigned to PCI devices - i.e. the memory and prefetch regions, as 374 passed to pci_set_region(). 375 376config PCIE_ECAM_SIZE 377 hex 378 default 0x10000000 379 help 380 This is the size of memory-mapped address of PCI configuration space, 381 which is only available through the Enhanced Configuration Access 382 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 383 so a default 0x10000000 size covers all of the 256 buses which is the 384 maximum number of PCI buses as defined by the PCI specification. 385 386endmenu 387