1*f3a7b953SNobuhiro Iwamatsu #ifndef _ASM_CPU_SH7706_H_ 2*f3a7b953SNobuhiro Iwamatsu #define _ASM_CPU_SH7706_H_ 3*f3a7b953SNobuhiro Iwamatsu 4*f3a7b953SNobuhiro Iwamatsu #define CACHE_OC_NUM_WAYS 4 5*f3a7b953SNobuhiro Iwamatsu #define CCR_CACHE_INIT 0x0000000D 6*f3a7b953SNobuhiro Iwamatsu 7*f3a7b953SNobuhiro Iwamatsu /* MMU and Cache control */ 8*f3a7b953SNobuhiro Iwamatsu #define MMUCR 0xFFFFFFE0 9*f3a7b953SNobuhiro Iwamatsu #define CCR 0xFFFFFFEC 10*f3a7b953SNobuhiro Iwamatsu 11*f3a7b953SNobuhiro Iwamatsu /* PFC */ 12*f3a7b953SNobuhiro Iwamatsu #define PACR 0xA4050100 13*f3a7b953SNobuhiro Iwamatsu #define PBCR 0xA4050102 14*f3a7b953SNobuhiro Iwamatsu #define PCCR 0xA4050104 15*f3a7b953SNobuhiro Iwamatsu #define PETCR 0xA4050106 16*f3a7b953SNobuhiro Iwamatsu 17*f3a7b953SNobuhiro Iwamatsu /* Port Data Registers */ 18*f3a7b953SNobuhiro Iwamatsu #define PADR 0xA4050120 19*f3a7b953SNobuhiro Iwamatsu #define PBDR 0xA4050122 20*f3a7b953SNobuhiro Iwamatsu #define PCDR 0xA4050124 21*f3a7b953SNobuhiro Iwamatsu 22*f3a7b953SNobuhiro Iwamatsu /* BSC */ 23*f3a7b953SNobuhiro Iwamatsu #define FRQCR 0xffffff80 24*f3a7b953SNobuhiro Iwamatsu #define BCR1 0xffffff60 25*f3a7b953SNobuhiro Iwamatsu #define BCR2 0xffffff62 26*f3a7b953SNobuhiro Iwamatsu #define WCR1 0xffffff64 27*f3a7b953SNobuhiro Iwamatsu #define WCR2 0xffffff66 28*f3a7b953SNobuhiro Iwamatsu #define MCR 0xffffff68 29*f3a7b953SNobuhiro Iwamatsu 30*f3a7b953SNobuhiro Iwamatsu /* SDRAM controller */ 31*f3a7b953SNobuhiro Iwamatsu #define DCR 0xffffff6a 32*f3a7b953SNobuhiro Iwamatsu #define RTCSR 0xffffff6e 33*f3a7b953SNobuhiro Iwamatsu #define RTCNT 0xffffff70 34*f3a7b953SNobuhiro Iwamatsu #define RTCOR 0xffffff72 35*f3a7b953SNobuhiro Iwamatsu #define RFCR 0xffffff74 36*f3a7b953SNobuhiro Iwamatsu #define SDMR 0xFFFFD000 37*f3a7b953SNobuhiro Iwamatsu #define CS3_R 0xFFFFE460 38*f3a7b953SNobuhiro Iwamatsu 39*f3a7b953SNobuhiro Iwamatsu /* SCIF */ 40*f3a7b953SNobuhiro Iwamatsu #define SCSMR_2 0xA4000150 41*f3a7b953SNobuhiro Iwamatsu #define SCIF0_BASE SCSMR_2 42*f3a7b953SNobuhiro Iwamatsu 43*f3a7b953SNobuhiro Iwamatsu /* Timer */ 44*f3a7b953SNobuhiro Iwamatsu #define TSTR0 0xFFFFFE92 45*f3a7b953SNobuhiro Iwamatsu #define TSTR TSTR0 46*f3a7b953SNobuhiro Iwamatsu #define TCNT0 0xFFFFFE98 47*f3a7b953SNobuhiro Iwamatsu #define TCR0 0xFFFFFE9C 48*f3a7b953SNobuhiro Iwamatsu 49*f3a7b953SNobuhiro Iwamatsu /* On chip oscillator circuits */ 50*f3a7b953SNobuhiro Iwamatsu #define WTCNT 0xFFFFFF84 51*f3a7b953SNobuhiro Iwamatsu #define WTCSR 0xFFFFFF86 52*f3a7b953SNobuhiro Iwamatsu 53*f3a7b953SNobuhiro Iwamatsu #endif /* _ASM_CPU_SH7706_H_ */ 54