1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 3819833afSPeter Tyser * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5819833afSPeter Tyser */ 6819833afSPeter Tyser 7819833afSPeter Tyser #ifndef _ASM_CPU_SH4_H_ 8819833afSPeter Tyser #define _ASM_CPU_SH4_H_ 9819833afSPeter Tyser 10819833afSPeter Tyser /* cache control */ 11819833afSPeter Tyser #define CCR_CACHE_STOP 0x00000808 12819833afSPeter Tyser #define CCR_CACHE_ENABLE 0x00000101 13819833afSPeter Tyser #define CCR_CACHE_ICI 0x00000800 14819833afSPeter Tyser 15819833afSPeter Tyser #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 16819833afSPeter Tyser 17819833afSPeter Tyser #if defined (CONFIG_CPU_SH7750) || \ 18819833afSPeter Tyser defined(CONFIG_CPU_SH7751) 19819833afSPeter Tyser #define CACHE_OC_WAY_SHIFT 14 20819833afSPeter Tyser #define CACHE_OC_NUM_ENTRIES 512 21819833afSPeter Tyser #else 22819833afSPeter Tyser #define CACHE_OC_WAY_SHIFT 13 23819833afSPeter Tyser #define CACHE_OC_NUM_ENTRIES 256 24819833afSPeter Tyser #endif 25819833afSPeter Tyser #define CACHE_OC_ENTRY_SHIFT 5 26819833afSPeter Tyser 27819833afSPeter Tyser #if defined (CONFIG_CPU_SH7750) || \ 28819833afSPeter Tyser defined(CONFIG_CPU_SH7751) 29819833afSPeter Tyser # include <asm/cpu_sh7750.h> 30819833afSPeter Tyser #elif defined (CONFIG_CPU_SH7722) 31819833afSPeter Tyser # include <asm/cpu_sh7722.h> 32819833afSPeter Tyser #elif defined (CONFIG_CPU_SH7723) 33819833afSPeter Tyser # include <asm/cpu_sh7723.h> 34bead86a8SNobuhiro Iwamatsu #elif defined (CONFIG_CPU_SH7724) 35bead86a8SNobuhiro Iwamatsu # include <asm/cpu_sh7724.h> 362a57e7ecSNobuhiro Iwamatsu #elif defined (CONFIG_CPU_SH7734) 372a57e7ecSNobuhiro Iwamatsu # include <asm/cpu_sh7734.h> 381a2621baSYoshihiro Shimoda #elif defined (CONFIG_CPU_SH7752) 391a2621baSYoshihiro Shimoda # include <asm/cpu_sh7752.h> 40*320cf350SYoshihiro Shimoda #elif defined (CONFIG_CPU_SH7753) 41*320cf350SYoshihiro Shimoda # include <asm/cpu_sh7753.h> 428e9c897bSYoshihiro Shimoda #elif defined (CONFIG_CPU_SH7757) 438e9c897bSYoshihiro Shimoda # include <asm/cpu_sh7757.h> 44819833afSPeter Tyser #elif defined (CONFIG_CPU_SH7763) 45819833afSPeter Tyser # include <asm/cpu_sh7763.h> 46819833afSPeter Tyser #elif defined (CONFIG_CPU_SH7780) 47819833afSPeter Tyser # include <asm/cpu_sh7780.h> 48819833afSPeter Tyser #elif defined (CONFIG_CPU_SH7785) 49819833afSPeter Tyser # include <asm/cpu_sh7785.h> 50819833afSPeter Tyser #else 51819833afSPeter Tyser # error "Unknown SH4 variant" 52819833afSPeter Tyser #endif 53819833afSPeter Tyser 54819833afSPeter Tyser #if defined(CONFIG_SH_32BIT) 55819833afSPeter Tyser #define PMB_ADDR_ARRAY 0xf6100000 56819833afSPeter Tyser #define PMB_ADDR_ENTRY 8 57819833afSPeter Tyser #define PMB_VPN 24 58819833afSPeter Tyser 59819833afSPeter Tyser #define PMB_DATA_ARRAY 0xf7100000 60819833afSPeter Tyser #define PMB_DATA_ENTRY 8 61819833afSPeter Tyser #define PMB_PPN 24 62819833afSPeter Tyser #define PMB_UB 9 /* Buffered write */ 63819833afSPeter Tyser #define PMB_V 8 /* Valid */ 64819833afSPeter Tyser #define PMB_SZ1 7 /* Page size (upper bit) */ 65819833afSPeter Tyser #define PMB_SZ0 4 /* Page size (lower bit) */ 66819833afSPeter Tyser #define PMB_C 3 /* Cacheability */ 67819833afSPeter Tyser #define PMB_WT 0 /* Write-through */ 68819833afSPeter Tyser 69819833afSPeter Tyser #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) 70819833afSPeter Tyser #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) 71819833afSPeter Tyser #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) 72819833afSPeter Tyser #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ 73819833afSPeter Tyser ((ppn << PMB_PPN) | (ub << PMB_UB) | \ 74819833afSPeter Tyser (v << PMB_V) | (sz1 << PMB_SZ1) | \ 75819833afSPeter Tyser (sz0 << PMB_SZ0) | (c << PMB_C) | \ 76819833afSPeter Tyser (wt << PMB_WT)) 77819833afSPeter Tyser #endif 78819833afSPeter Tyser 79819833afSPeter Tyser #endif /* _ASM_CPU_SH4_H_ */ 80