1 /* 2 * (C) Copyright 2007 3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <asm/io.h> 11 #include <asm/processor.h> 12 #include <asm/system.h> 13 14 #define CACHE_VALID 1 15 #define CACHE_UPDATED 2 16 17 static inline void cache_wback_all(void) 18 { 19 unsigned long addr, data, i, j; 20 21 for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { 22 for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { 23 addr = CACHE_OC_ADDRESS_ARRAY 24 | (j << CACHE_OC_WAY_SHIFT) 25 | (i << CACHE_OC_ENTRY_SHIFT); 26 data = inl(addr); 27 if (data & CACHE_UPDATED) { 28 data &= ~CACHE_UPDATED; 29 outl(data, addr); 30 } 31 } 32 } 33 } 34 35 #define CACHE_ENABLE 0 36 #define CACHE_DISABLE 1 37 38 int cache_control(unsigned int cmd) 39 { 40 unsigned long ccr; 41 42 jump_to_P2(); 43 ccr = inl(CCR); 44 45 if (ccr & CCR_CACHE_ENABLE) 46 cache_wback_all(); 47 48 if (cmd == CACHE_DISABLE) 49 outl(CCR_CACHE_STOP, CCR); 50 else 51 outl(CCR_CACHE_INIT, CCR); 52 back_to_P1(); 53 54 return 0; 55 } 56 57 void flush_dcache_range(unsigned long start, unsigned long end) 58 { 59 u32 v; 60 61 start &= ~(L1_CACHE_BYTES - 1); 62 for (v = start; v < end; v += L1_CACHE_BYTES) { 63 asm volatile ("ocbp %0" : /* no output */ 64 : "m" (__m(v))); 65 } 66 } 67 68 void invalidate_dcache_range(unsigned long start, unsigned long end) 69 { 70 u32 v; 71 72 start &= ~(L1_CACHE_BYTES - 1); 73 for (v = start; v < end; v += L1_CACHE_BYTES) { 74 asm volatile ("ocbi %0" : /* no output */ 75 : "m" (__m(v))); 76 } 77 } 78